LPC18S50 datasheet(126/151 Pages) NXP

126 / 151 page

LPC18S50_S30_S10

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 23 February 2015

126 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

12. ADC/DAC electrical characteristics

[1]

The ADC is monotonic, there are no missing codes.

[2]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 39.

[3]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 39.

[4]

The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 39.

[5]

The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 39.

[6]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 39.

[7]

Tamb = 25 C.

[8]

Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs  Cia).

Table 32.

ADC characteristics

VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

VIA

analog input voltage

VDDA(3V3)

Cia

analog input capacitance

differential linearity error

2.7 V

 V

DDA(3V3)  3.6 V

[1][2] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

LSB

EL(adj)

integral non-linearity

2.7 V

 V

DDA(3V3)  3.6 V

[3] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.5

LSB

offset error

2.7 V

 V

DDA(3V3)  3.6 V

[4] -

0.15

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

0.15

LSB

gain error

2.7 V

 V

DDA(3V3)  3.6 V

[5] -

0.3

2.2 V

 V

DDA(3V3) < 2.7 V

0.35

absolute error

2.7 V

 V

DDA(3V3)  3.6 V

[6] -

3-

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

4-

LSB

Rvsi

voltage source interface

resistance

see Figure 40

1/(7

 f

clk(ADC)

 C

ia)



input resistance

[7][8] --

1.2



fclk(ADC) ADC clock frequency

4.5

MHz

sampling frequency

10-bit resolution; 11 clock

cycles

400

kSamples/s

2-bit resolution; 3 clock

cycles

1.5

MSamples/s

LPC18S50 Datasheet(PDF) 126 Page - NXP Semiconductors

LPC18S50 Datasheet(HTML) 126 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL