LPC18S50 datasheet(128/151 Pages) NXP

128 / 151 page

LPC18S50_S30_S10

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 23 February 2015

128 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

[1]

In the DAC CR register, bit BIAS = 0 (see the LPC18xx user manual).

[2]

Settling time is calculated within 1/2 LSB of the final value.

Rs < 1/((7

 f

clk(ADC)  Cia)  2 k

Fig 40. ADC interface to pins

LPC18xx

ADC0_n/ADC1_n

Cia = 2 pF

Rvsi

VSS

VEXT

002aag697

ADC

COMPARATOR

2 kΩ (analog pin)

2.2 kΩ (multiplexed pin)

Table 33.

DAC characteristics

VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

differential linearity error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

LSB

EL(adj)

integral non-linearity

code = 0 to 975

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

1.0

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.5

LSB

offset error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.8

LSB

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

LSB

gain error

2.7 V

 V

DDA(3V3)  3.6 V

[1] -

0.3

2.2 V

 V

DDA(3V3) < 2.7 V

1.0

load capacitance

200

load resistance



settling time

[1]

0.4



LPC18S50 Datasheet(PDF) 128 Page - NXP Semiconductors

LPC18S50 Datasheet(HTML) 128 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL