LPC18S50 datasheet(135/151 Pages) NXP

135 / 151 page

LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

135 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

On the LPC18S50/S30/S10, USBn_VBUS pins are 5 V tolerant only when VDDIO is

applied and at operating voltage level. Therefore, if the USBn_VBUS function is

connected to the USB connector and the device is self-powered, the USBn_VBUS pins

must be protected for situations when VDDIO = 0 V.

If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be

connected directly to the VBUS pin on the USB connector.

For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn_VBUS

pins, precautions must be taken to reduce the voltage to below 3.6 V, which is the

maximum allowable voltage on the USBn_VBUS pins in this case.

One method is to use a voltage divider to connect the USBn_VBUS pins to VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be

greater than 0.7VDDIO to indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operating conditions

VBUSmax = 5.25 V

VDDIO = 3.6 V,

the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

For bus-powered devices, a regulator powered by USB can provide 3.3 V to VDDIO

whenever bus power is present and ensure that power to the USBn_VBUS pins is always

present when the 5 V VBUS signal is applied. See Figure 47.

Remark: Applying 5 V to the USBn_VBUS pins for a short time while the regulator ramps

up might compromise the long-term reliability of the part but does not affect its function.

Fig 46. USB interface on a self-powered device where USBn_VBUS = 5 V

LPC18xx

VDDIO

USB-B

connector

USBn_VBUS

VBUS

USB

aaa-013015

LPC18S50 Datasheet(PDF) 135 Page - NXP Semiconductors