Electronic Components Datasheet Search
  English  ▼

X  

PC87303 Datasheet(PDF) 110 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87303
Description  PC87303VUL SuperI/OTM Sidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, IEEE 1284 Parallel Port, and IDE Inter
PDF  114 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87303 Datasheet(HTML) 110 Page - National Semiconductor (TI)

Back Button PC87303 Datasheet HTML 106Page - National Semiconductor (TI) PC87303 Datasheet HTML 107Page - National Semiconductor (TI) PC87303 Datasheet HTML 108Page - National Semiconductor (TI) PC87303 Datasheet HTML 109Page - National Semiconductor (TI) PC87303 Datasheet HTML 110Page - National Semiconductor (TI) PC87303 Datasheet HTML 111Page - National Semiconductor (TI) PC87303 Datasheet HTML 112Page - National Semiconductor (TI) PC87303 Datasheet HTML 113Page - National Semiconductor (TI) PC87303 Datasheet HTML 114Page - National Semiconductor (TI)  
Zoom Inzoom in Zoom Outzoom out
 110 / 114 page
background image
100 Electrical Characteristics (Continued)
10215 Enhanced Parallel Port Timing
Symbol
Parameter
Conditions
Min
Max
Units
tWW
WRITE Active from WR Active (Note 1)
45
ns
tWST
DSTRB or ASTRB Active from WR Active
EEP 17
45
ns
(Notes 1 2)
EPP 19
65
ns
tWEST
DSTRB or ASTRB Active after
EPP 17
0
ns
WRITE Active
EPP 19
10
ns
tWPDh
PD0 – PD7 Hold after DSTRB or ASTRB
50
ns
Inactive
tHRW
IOCHRDY Active after WAIT Active (Note 3)
EPP 17
40
ns
tWPDS
PD0 – PD7 Valid after WRITE Active
D0 – 7 is stable 15 ns
15
ns
before WR Active
tEPDW
80
ns
tEPDh
0ns
tZWSa
ZWS Valid after WR or RD Active
45
ns
tZWSh
ZWS Hold after WR or RD Inactive
0
ns
Note 1
tWST and tWW are valid in EPP 19 only if WAIT is low when WR becomes active else tWST and tWW are measured from WAIT
Note 2
The PC87303 design guarantees that WRITE will not change from low to high before DSTRB or ASTRB goes from low to high
Note 3
In EPP 19 IOCHRDY is measured from WR or RD
TLC12074 – 78
FIGURE 10-21 Enhanced Parallel Port Timing
110



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com