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PC87303 Datasheet(PDF) 106 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 106 Page - National Semiconductor (TI) |
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106 / 114 page ![]() 100 Electrical Characteristics (Continued) 10282 ECP Symbol Parameter Min Max Units tKIP PDACK Inactive Pulse Width 25 ns tKKP PDACK Active Pulse Width 65 ns tKQP PDACK Active Edge to PDRQ Inactive (Notes 2 3) 65 a (6x32xtCP)ns tQKP PDRQ to PDACK Active Edge 10 ns tQPP PDRQ Period 330 m s tQQP PDRQ Inactive Non-Burst Pulse Width 300 400 ns tQRP PDRQ to RD WR Active 15 ns tRQP RD or WR Active Edge to PDRQ Inactive (Note 1) 65 ns tTQP TC Active Edge to PDRQ Inactive 75 ns tTT TC Active Pulse Width 50 ns Note 1 The active edge of RD or WR and TC is recognized only when PDACK is active Note 2 One DMA transaction takes six clock cycles Note 3 tCP is defined in Section 1022 Clock Timing TLC12074 – 69 FIGURE 10-12b ECP DMA Timing 106 |
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