TAS5721 datasheet(22/78 Pages) TI1

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TAS5721

SLOS739A – JULY 2012 – REVISED MARCH 2016

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Functional Block Diagram (continued)

Figure 49. DAP Process Structure

9.3 Feature Description

9.3.1 Power Supply

To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply.

The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal

voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a

floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry

requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins

(BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD

voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as

possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap

capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X)

and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the

output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical

Application section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These capacitors

ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET

(LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is

decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical

Application section.

The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging.

TAS5721 Datasheet(PDF) 22 Page - Texas Instruments