TAS5721 datasheet(10/78 Pages) TI1

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SCL

SDA

w(H)

w(L)

su1

T0027-01

w(RST)

RST

d(I2C_ready)

System Initialization.

Enable via I C.

T0421-01

I C Active

TAS5721

SLOS739A – JULY 2012 – REVISED MARCH 2016

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Serial Audio Port Timing (continued)

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8

Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with

recommended operating conditions (unless otherwise specified).

MIN

TYP

MAX

UNIT

LRCLK frequency

kHz

SCLK duty cycle

40%

50%

60%

LRCLK duty cycle

40%

50%

60%

SCLK rising edges between LRCLK rising edges

SCLK

edges

t(edge)

LRCLK clock edge with respect to the falling edge of SCLK

–1/4

1/4

SCLK

period

tr/tf

Rise/fall time for SCLK/LRCLK

LRCLK allowable drift before LRCLK reset

MCLK

Periods

NOTE: On power up, it is recommended that the TAS5721 RST be held LOW for at least 100

μs after DVDD has reached 3

NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100

μs after PDN is

deasserted (HIGH).

Figure 1. Reset Timing

Figure 2. SCL and SDA Timing

TAS5721 Datasheet(PDF) 10 Page - Texas Instruments

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