TAS5721 datasheet(23/78 Pages) TI1

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TAS5721

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SLOS739A – JULY 2012 – REVISED MARCH 2016

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Feature Description (continued)

9.3.2 I2C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the

Typical Application section in order to set the I2C address. Pulling this pin HIGH through the resistor results in

setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the

address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault

notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's

default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, over-

temperature, over-voltage lock-out, and under-voltage lock-out.

9.3.3 Device Protection System

9.3.3.1 Overcurrent (OC) Protection With Current Limiting

The device has independent, fast reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored by a protection system. If the high-current condition situation persists, a

protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-

Z) state. After the power stage enters into this state, the power stage will attempt to restart after a period of time

defined in register 0x1C. If the high-current condition persists, the device will begin the shutdown and retry

sequence again. The device will return to normal operation once the fault condition is removed. Current limiting

and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-

bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.

9.3.3.2 Overtemperature Protection

The TAS5721 has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. The TAS5721 recovers

automatically once the temperature drops approximately 30 °C.

9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5721 fully protect the device in any power-up/down and brownout situation.

While powering up, the POR circuit ensures that all circuits are fully operational when the PVDD and AVDD

supply voltages reach 4.1 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a

supply voltage drop below the UVP threshold on AVDD or on either PVDD pin results in all half-bridge outputs

immediately being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being

asserted low.

9.3.4 Clock, Auto Detection, and PLL

The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the Clock Control Register section.

The TAS5721 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the clock control register.

TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)

and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the

clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process,

the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting

process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

TAS5721 Datasheet(PDF) 23 Page - Texas Instruments

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