TAS5721 datasheet(29/78 Pages) TI1

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SCLK

32Clks

LRCLK(NoteReversedPhase)

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelI S(PhilipsFormat)StereoInput

T0034-01

MSB

LSB

SCLK

TAS5721

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SLOS739A – JULY 2012 – REVISED MARCH 2016

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Command sequences for updating DAP coefficients can be summarized as follows:

Bank switching disabled (default): DAP coefficient writes take immediate effect and are not

influenced by subsequent sample rate changes.

Bank switching enabled:

(a)

Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.

(b)

Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.

(c)

Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.

(d)

Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.

9.3.12 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in

16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

9.3.12.1 Serial Interface Control and Timing

The I2S mode is set by writing to register 0x04.

9.3.12.1.1

2S Timing

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data bit positions.

NOTE: All data presented in 2s-complement form with MSB first.

Figure 56. I2S 64-fS Format

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