TAS5721 datasheet(35/78 Pages) TI1

35 / 78 page

CH1_audio

CH3_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-04

D (S )

–

B (

)

R–

C (S+)

A (L+)

CH1_audio

CH3_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-03

D (S )

–

B (

)

R–

C (S+)

A (L+)

CH1_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-02

D (

)

R–

B (L )

–

C (R+)

A (L+)

CH1_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-01

D (

)

R–

B (L )

–

C (R+)

A (L+)

TAS5721

www.ti.com

SLOS739A – JULY 2012 – REVISED MARCH 2016

Product Folder Links: TAS5721

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The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail,

combining this with the built in click and pop reduction circuit, the DirectPath amplifier requires no output dc

blocking capacitors.

The bottom block diagram and waveform of Figure 66 illustrate the ground-referenced headphone and line driver

architecture. This is the architecture of the TAS5721.

9.4 Device Functional Modes

9.4.1 Output Mode and MUX Selection

The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge

tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate

either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the

majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced

complexity, the figure below outlines both the register settings and the output configurations required to set the

device up for operation in these various modes.

The output configuration quick reference table below highlights the controls that are required to configure the

device for various operational modes. Please note that other controls, which are not directly related to the output

configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to

be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these

considerations, in addition to start and stop time and others. Please consult the respective registers for these

controls to optimize for various other performance parameters and use cases.

Table 1. Output Configuration Quick Reference

OUTPUT

CONFIGURATION

MODULATION MODE

BLOCK DIAGRAM

2.0 (Stereo BTL)

AD for Both Outputs

0x20[23] = 0

0x20[19] = 0

0x20[15:8] = 0x77

0x05[7] = 0

0x05[2] = 0

0x25[23:8] = 0x0213

0x1A[7:0] = 0x0F

BD for Both Outputs

0x20[23] = 1

0x20[19] = 1

0x20[15:8] = 0x77

0x05[7] = 0

0x05[2] = 0

0x25[23:8] = 0x0213

0x1A[7:0] = 0x0A

Single Device 2.1

(Stereo Single

Ended + Mono

BTL)

Note: In these

described

configurations, the

polarity of the

signal being sent to

SPK_OUTB is

inverted. For this

reason, care

should be taken to

ensure that the

speakers are

connected as

shown in the block

diagram.

AD for Both SE Outputs

AD for Single BTL

Output

0x20[23] = 0

0x20[19] = 0

0x20[3] = 0

0x05[7] = 1

0x05[2] = 1

0x25[23:8] = 0x0132

0x1A[7:0] = 0x95

0x20[7:4] = 0x7

0x21[8] = 0

0x20[25] = 1

AD for both SE Outputs

BD for Single BTL

Output

0x20[23] = 0

0x20[19] = 0

0x20[3] = 1

0x05[7] = 1

0x05[2] = 1

0x25[23:8] = 0x0132

0x1A[7:0] = 0x95

0x20[7:4] = 0x7

0x21[8] = 0

0x20[25] = 1

TAS5721 Datasheet(PDF) 35 Page - Texas Instruments

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