TAS5721 datasheet(25/78 Pages) TI1

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TAS5721

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SLOS739A – JULY 2012 – REVISED MARCH 2016

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Feature Description (continued)

9.3.8 PBTL-Mode Support

The TAS5721 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected after

the LC filter. In order to put the part in PBTL configuration, the PWM output multiplexers should be updated to

set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also,

the PWM shutdown register (0x19) should be written with a value of 0x3A.

9.3.9 I2C Serial Control Interface

The TAS5721 DAP has a bidirectional inter-integrated circuit (I2C) interface that is compatible with the I2C bus

protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read

operations. This is a slave only device that does not support a multimaster bus environment or wait state

insertion. The control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation

(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.

9.3.9.1 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been

received when a stop command (or another start command) is received, the data received is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5721

also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for

that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the

data for all 16 subaddresses is successfully received by the TAS5721. For I2C sequential write transactions, the

subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or

start is transmitted, determines how many subaddresses are written. As was true for random addressing,

sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to

the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;

only the incomplete data is discarded.

9.3.9.2 Single-Byte Write

As shown in Figure 50, a single-byte data write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device

address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the

address byte or bytes corresponding to the TAS5721 internal memory address being accessed. After receiving

the address byte, the TAS5721 again responds with an acknowledge bit. Next, the master device transmits the

data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5721 again

responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-

byte data write transfer.

TAS5721 Datasheet(PDF) 25 Page - Texas Instruments

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