EM6517 datasheet(10/64 Pages) EMMICRO

10 / 64 page

EM6517

03/02 REV. C/448

 2002, EM Microelectronic-Marin SA

www.emmicroelectronic.com

5.3.2 OR -Type Reset function

If wanted, needs to be chosen with the metal 1 option settings (MFP uses default NAND option). Any one of the

port A inputs can trigger a reset. Following formula is applicable :

InpResPA

= InpResPA[0] + InpResPA[1] + InpResPA[2] + InpResPA[3]

InpRes1PA[n] InpRes2PA[n] InpResPA[n]

00VSS

PA[n]

not PA[n]

11VDD

n = 0 to 3

i.e. ; - no reset if all InpResPA[n] = VSS.

- Don't care function on a single bit with

its InpResPA[n] = Vss.

- Always Reset if any InpResPA[3:0] = VDD

5.4 Digital Watchdog Timer Reset

The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will

generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by

activating an inhibit digital watchdog bit (NoLogicWD) located in RegSysCntl3. At power up, and after any

system reset, the watchdog timer is activated.

If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset

signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the

watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a

system reset signal is generated.

The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and

timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer

operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode

for more than 2.5 seconds.

From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog

timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It

is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every

second.

It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the

counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into

the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system reset

which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.

Figure 10. Input Port A Reset Structure

1 MUX

3 1 0

VSS

PA[3]

VDD

BIT

[0]

BIT

[1]

BIT

[2]

BIT

[3]

InpResPA

InpResPA[3]

InpRes2PA[3]

InpRes1PA[3]

Input Port A Reset

Bit[2] Selection

Input Port A Reset

Bit[1] Selection

Input Port A Reset

Bit[0] Selection

Input Port A Reset

Bit[3] Selection

Input

Reset

from

Port A

EM6517 Datasheet(PDF) 10 Page - EM Microelectronic - MARIN SA

EM6517 Datasheet(HTML) 10 Page - EM Microelectronic - MARIN SA

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL