EM6517 datasheet(39/64 Pages) EMMICRO

39 / 64 page

EM6517

03/02 REV. C/448

 2002, EM Microelectronic-Marin SA

www.emmicroelectronic.com

13 Interrupt Controller

The EM6517 has 12 different interrupt request sources each of which is maskable. 4 of them are coming from

extarnal sources and 8 from internal.

External(4)

- Port A,

PA[3] .. PA[0] inputs

Internal(8)

- Prescaler

Ck[1], 32 Hz / 8 Hz

- 10-bit Counter

Count to 0, Count equal to Compare

- EEPROM

End of writing operation

- ADC

End of conversion

- VLD

End of measure

- SWB (non-maskable)

SWB empty in interactive mode

Note

: the interrupt request from Serial Output Buffer (SWBEmpty) in interactive mode can not be masked in

opposition to the others and goes directly to the CPU.

For interrupt requests except SWBEmpty interrupt :

To be able to send an interrupt to the CPU, at least one of the interrupt request flags must ‘1’ (IRQxx)

and the general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt

request flags can only be set high by a positive edge on the IRQxx data flip-flop while the corresponding mask

At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any

interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.

After each read operation on the interrupt request registers RegIRQ1, RegIRQ2 or RegIRQ3 the contents of the

addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was

more than one IRQ to treat. Each interrupt request flag may also be reset individually by writing 1 into it .

Interrupt handling priority must be resolved through software by deciding which register and which flag inside

the register need to be serviced first.

Since the CPU has only one interrupt subroutine and the IRQxx registers are cleared after reading, the CPU

does not miss any interrupt request which comes during the interrupt service routine. If any occurs during this

time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine.

Figure 29. Interrupt Controller Block Diagram

Interrupt Request

Capture Register

12 Input-OR

Read

ClrIntBit

Reset

General

INT En

IRQ to µP

One of these Blocks for each IRQ

DB[n]

IRQxx

SWBEmpty

Write

Mask

Write

Halt

SWBAuto

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