IC-GD datasheet(47/55 Pages) ICHAUS

47 / 55 page

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 47/55

ing the reference value. The reference value as such is

not reached.

CNT_RAR_x

LK - P

RW - 0

Activates the counter reset when the reference value

is reached

Table 54: Reset at reference

direction. This function is supported by the following

modes:

• Single: Pulse counter

• Dual: Pulse counter with trigger

• Dual: Pulse counter with reset

• Dual: Pulse counter with gate

CNT_DNU_x

LK - P

RW - 0

up (where available)

down (where available)

Table 55: Counting direction

that count pulses, both in single and dual mode. It en-

ables selecting whether only one type of edge (rising or

falling) or both are counted. In the first case, the edge

is selected via register DIO_INV_x.

CNT_CBE_x

LK - P

RW - 0

Only one type of edge is counted (rising or falling, cf.

DIO_INV_x)

Both edges are counted (rising and falling)

Table 56: Edges

channel. The first counter can be compared with both

reference values and the equality is indicated via the

respective status bit. This is possible both in single

and in dual mode. The possibility to prevent several

interrupts via register CNT_DCB_1 remains for both

comparisons separately.

This mode is not possible if the second counter is in

PWM mode, since the reference register is required

there. The second counter can be operated as a clas-

sic counter, with the restriction that its reference register

can be used twice but can only have one value. The

second channel can carry out every function without

restriction.

CNT_E2R_1

LK - P

RW - 0

Additionally acativates the comparison of the first

counter with a second reference value

Table 57: Second reference

CNT_SEL_x in single-Mode

LK - P

RW - 000

000

Pulse counter

001

Time measurement period

010

Time measurement pulse width

011

PWM (output)

Table 58: Mode selection in single-mode

CNT_SEL_x in dual-mode

LK - P

RW - 000

000

Pulse counter with trigger

001

Pulse counter with reset

010

Pulse counter with gate

011

Pulse counter with direction signal

100

Time-measurement edge between channel 1 and 2

101

Incremental encoder single

110

Incremental encoder dual

111

Incremental encoder quadruple

Table 59: Mode selection in dual-mode

CNT_DUAL_1

LK - P

RW - 0

Activates the dual-mode: both inputs combined

control one counter; to be configured for channel 1;

both channels must be configured as counters

Table 60: Selection single-/dual-mode

Counter PWM

The following registers refer to the function of the

counter in PWM mode. This register block shares its

functions with other modes. It is only valid if the PWM

counter is also selected in register IO_SEL_xP.

PWM_HS_x

LK - P

RW - 0

LOW-SPEED MODE, see Tab. 75

HIGH-SPEED MODE, see Tab. 75

Table 61: Selection low-speed/high-speed

the PWM. When switching on the PWM, a (usually) long

activation pulse is generated before the PWM starts.

An inversion at the input and output is still possible.

PWM_AZP_x

LK - P

RW - 0

PWM generates an activation pulse

Table 62: PWM activation pulse

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