IC-GD datasheet(50/55 Pages) ICHAUS

50 / 55 page

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 50/55

AI_LOWER_x

LK-PS

RW - 0x8000

bits 15:0

Lower limit (last valid value)

Table 71: Lower limit

AI_UPPER_x

LK-PS

RW - 0x7FFF

bits 15:0

Upper limit (last valid value)

Table 72: Upper limit

SPV_INT

of an error, the relevant bit is set to ’1’ and remains

set until the register is read via SPI. The register is

shown in figure 7. It is not linked to the others registers

though.

SPV_INT

R - 0x00

ST_PLL

Status PLL

ST_VBG

Status band-gap voltage VBG

ST_VPA

Status internal supply voltage VDP

ST_VPD

Status internal supply voltage VPD

Table 73: Internal monitor bits status

SET_CNT_x

counter to a specific value. Via the register communica-

tion, the register can be set both in single or continuous

mode. When writing the last register byte, the written

16/32-bit-wide word is taken as a whole. In regular

counter modes, only setting the register as a whole is

useful. In PWM mode or with activation pulse mode,

either the entire register or only the lower half (bits 15:0)

can be set. Except for this, a partial writing of the regis-

ter is not possible. The meaning of the register depends

on the selected mode (see chapter ’Counter’).

SET_CNT_x

W - 0x00000000

bits 31:0

Counter value

Table 74: Set counter

REF_CNT_x

erence value. Via the register communication, the

mode. When writing on the last register byte, the written

16/32-bit-wide word is taken as a whole. It is possible

to set the register as a whole (bits 31:0) or to set only

the lower half (bits 15:0). In PWM mode, it is useful

to set only the lower half (bits 15:0). Except for this, a

partial writing of the register is not possible. The mean-

ing of the register depends on the selected mode (see

chapter ’Counter’).

REF_CNT_x

RW -

0x00000000

Bits 31:0

Reference value

Table 75: Set counter reference

Monitoring

The bits of the monitoring register signal errors of indi-

vidual supply voltages and overtemperature. In case

of an error, the relevant bit is set to ’1’ and remains set

until the register is read out via the SPI. This enables

to detect voltage dips that occurred temporarily.

SPV_REG

R - 0x00

ST_VB

Supply voltage VB

ST_VNB

Supply voltage VNB

ST_VDA

Supply voltage VDA

ST_BIAS

Bias (RREF)

ST_CT1

Chip temperature 1 (cf. Toff1)

ST_CT2

Chip temperature 2 (cf. Toff2)

ST_CONF

Configuration (CRC error)

ST_CALIB

Configuration (CRC error)

Table 76: Supervisory bits

EN_SPV_IRQ

LK - /

RW - 0x00

EN_VB

VB monitor activation

EN_VNB

VNB monitor activation

EN_VDA

VDA monitor activation

EN_BIAS

Bias monitor activation

EN_CT1

CT1 monitor activation

EN_CT2

CT2 monitor activation

EN_CONF

Configuration monitor activation

EN_CALIB

Configuration monitor activation

Table 77: Supervisory bits activation

EN_IRQ_FLAG_REG

The bits in register EN_IRQ_FLAG_REG activate the

relevant bits in register IRQ_FLAG individually.

EN_IRQ_FLAG_REG

LK - /

RW - 0x0000

bit 15:0

Activates individual bits of register

IRQ_FLAG_REG(15:0)

Table 78: IRQ flag activation

DATA_xS

Registers DATA_xS contain data of the secondary chan-

nel. If the secondary channel operates as input, the

current values of the secondary channel can be read. If

the secondary channel operates as output, output data

can be written to the register. The communication pro-

ceeds via the regular register communication in single

or continuous mode.

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