IC-GD datasheet(51/55 Pages) ICHAUS

51 / 55 page

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 51/55

Applying for modes using 16-bit wide values:

When the data is read, the lower half of the register

word is latched to ensure that a valid word is read out.

When the data is written, the word is assumed as a

whole only after transmission of the lower half.

Applying for modes using 8 bit wide values:

The values must be written or read left-aligned, i.e. only

the bits 15:8 are used.

Usually, data is formatted identically to the data of the

primary channels.

DATA_xS

(*) RW - 0x0000

Secondary channel data (in/out)

Table 79: Secondary channel data

EN_UCM

Via register EN_UCM, SPI communication can be se-

lected between FPGA and µC mode. In FPGA mode,

the bit is ’0’ for all iCs. In µC mode, the bit is ’0’ for all

iCs except the last iC which must be ’1’.

EN_UCM

LK - /

RW - 0

FPGA modus: no additional delay

µC mode: additional clocks

Table 80: µC mode

EN_SPI_WD

used for SPI communication. If the watchdog is active

and no valid SPI communication takes place during a

determined period, the watchdog resets the chip. De-

tails can be found in chapter ’Startup, reset, watchdogs,

and EEPROM’.

EN_SPI_WD

LK - /

RW - 0

SPI watchdog inactive

SPI watchdog active

Table 81: SPI watchdog

DIS_SPI_x

When required, register DIS_SPI_x deactivates the pro-

cess data of the SPI communication for channel x. This

bit affects only the opcodes "Process Data 1/2/1&2". If

a channel is not used, it does not require time by setting

this bit during the SPI communication. An interesting

use is in broadcast operation with chains of iCs with

partially unused channels.

DIS_SPI_x

LK - P

RW - 0

Channel x active

Channel x inactive

Table 82: Disable SPI CH_x

DIS_CAL

When required, register DIS_CAL deactivates the cali-

bration of the chip. This register is checked only when

the chip starts up, therefore its state must be stored in

the EEPROM.

DIS_CAL

LK-PS

RW - 0

Calibration active

Calibration inactive

Table 83: Disable channel calibration

EN_SS

When required, register EN_SS activates the spectrum

spread of the internal oscillator.

EN_SS

LK - /

RW - 0

Spread spectrum inactive

Spread spectrum active

Table 84: Enable spread spectrum

VDA_VB

When the digital output is not used, register VDA_VB

enables to omit the 24 V digital supply voltage. Instead,

the analog voltage VB can be connected to the pin VDA.

In this case this bit should be set to adapt the internal

voltage monitoring accordingly.

VDA_VB

LK - /

RW - 0

VDA = 24 V, digital output used

VDA = VB, digital output not used

Table 85: VDA at VB

SEL_ETK

are used for the TK compensation and chip-temper-

ature calibration (ATK, AITK, and AOCT). These can

either be taken from the internal chip, if they were spec-

ified in the chip production process, or they can be

taken from the external EEPROM where they can be

specified subsequently. Independent of their use, the

values that are stored in the EEPROM are used for the

calculation of the CRC value.

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