IC-GD datasheet(52/55 Pages) ICHAUS

52 / 55 page

prel

imin

ary

prel

imin

ary

iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 52/55

SEL_ETK

LK - /

RW - 0

Internal calibration values are used

External calibration values are used

Table 86: SEL_ETK

SPI_LOCK_RESET

It possesses multiple functions that can be activated by

writing keywords: When writing 0xCA, a software reset

is triggered – the chip restarts. When writing 0xA5, the

SPI access for all registers is enabled in accordance

with the register overview. Writing 0x00 (and further

bytes) disables writing access of the SPI to the configu-

ration registers marked with ’L’. After configuration, this

helps to prevent accidental writing on the configuration

registers in regular operation.

When writing 0xC5, the counter enables a one-shot

CH_STAT event (prevention of multiple interrupts at one

event). This only affects the counter if the bit CNT_DCB

is set.

Writing with 0xAA activates a special calibration mode

where registers that are usually inaccessible are addi-

tionally unlocked. In this process, the usually active

address translation is switched off so that some regis-

ters change their addresses. This function should only

be activated during calibration and only according to

the extent described in chapter ’Calibration’.

When reading, this register returns four bits of sta-

tus information. These bits are reset by read access

(RD+RST). The first status bit is set if an illegal read

access occured. The second status bit is set if an ille-

gal write access occured. This relates both to locked

registers and the access of non-existing addresses.

Note that a prefetching proceeds in mode

READ_REG_CONTINOUS. As a result, illegal read

accesses that already occur internally may be indicated

without being deliberately controlled by the SPI. The

third status bit indicates the condition of the lock.

(*) The initial state of this ’register’ depends on the va-

lidity of the configuration data. If a valid configuration is

stored in the EEPROM, the SPI is locked after starting

up the chip. If the configuration is invalid, the SPI is not

locked.

SPI_LOCK_RESET

RW+RST - (*)

bit 0 read

Status illegal read, 1 = detected

bit 1 read

Status illegal write, 1 = detected

bit 2 read

Status lock, 1 = locked

bit 3 read

Status calibration mode, 1 = active

bit 7:4 read

0000

0xCA write

Software reset

0xA5 write

Configuration register write enabled

0xC5 write

CNT_STAT_REARM: signle CH_STAT

counter event enabled (*)

0xAA write

Calibration mode enabled. Caution! Further

parts of the register map become invalid, see

section ’Calibration’.

0x00 write

Configuration register write disabled

Table 87: SPI lock/reset

(*) Unlocking refers to the following 4 states: overflow,

underflow, REF_1 reached, REF_2 reached.

TEMP_KSK

perature that is necessary for the thermocouple mea-

surement. The register can be written both in single

and continuous mode. It accepts its value internally

only when the writing process of the second half is com-

pleted so that a consistent value is processed. It can

only be written to as a whole.

TEMP_KSK

RW - 0x0BA6

( ˆ=25°C)

bits 15:0

Cold-position temperature,

0x0000 ˆ= 0K, 1 LSB ˆ= 0.1 K

Table 88: Cold-position temperature

CHIP_TEMP

R - /

bits 7:0

Chip temperature, 0x00 ˆ= -64 °C, 1 LSB ˆ= 1 °C

Table 89: Chip temperature

EN_DIAG

ment. The channel for analysis is selected via register

DIAG_SEL_CH. The result is continuously updated in

dance with the analog output. The first valid measure-

ment value must be waited for accordingly.

EN_DIAG

RW - 0

Diagnostic modus active

Table 90: Diagnostics channel selection

IC-GD Datasheet(PDF) 52 Page - IC-Haus GmbH

IC-GD Datasheet(HTML) 52 Page - IC-Haus GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL