IC-GD datasheet(31/55 Pages) ICHAUS

31 / 55 page

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 31/55

reading and writing data via I2C, e.g. to the EEPROM,

one has to poll for the end of this process before a new

I2C communication can be started.

In addition, the SPI provides opcodes as respective

SYNC signals (edges and channels) and opcodes

for fast reading of the registers CH_STAT_REG and

IRQ_FLAG_REG. Figure 5 shows the SPI communica-

tion.

The SPI is blocked during the startup (RDY = 0). No

communication is possible during this time. In normal

operation, 30 µs after the beginning of startup at the

latest (usually with the rising edge of NRES), NCS must

be high. Otherwise the iC performs a quickstart that

skips reading the EEPROM and the internal calibration

data. In this case, both CRC error bits are set (see

chapter Calibration).

Figure 3 shows the SPI timing. The given times are

listed under operating conditions.

Figure 4 shows by way of example a daisy chain of

three iCs with five active channels that are controlled by

a µC. The input data noted above the iCs are sampled

with the falling edge at NCS for all iCs simultaneously

and then clocked out via SPI. The output data written

by the SPI is noted below the iCs and is also output

simultaneously with the rising edge at NCS for all iCs

(for analog outputs: subsequently with the next refresh-

cycle).

SCLK

SDI

SDO

NCS

CSU

CSH

POmax

POT

POmin

POmax

ASIC n

ASIC n+1

VT()hi

VT()lo

Daisy chain example

Figure 3: SPI-Timing

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