AD7761 datasheet(37/76 Pages) AD

37 / 76 page

AD7761

Data Sheet

Rev. A | Page 36 of 75

SPI Reset Configuration

After a power-on or reset, the AD7761 default configuration is set

to the following low current consumption settings:

•

Low power mode with MCLK/32.

•

Interface configuration of DCLK = MCLK/8, header

output enabled, and CRC disabled.

•

Filter configuration of Channel Mode A and Channel Mode B

is set to sinc5 and decimation = ×1024. Channel mode

select is set to 0x00, and all channels are assigned to

Channel Mode A.

•

Channel configuration of Channel 0 to Channel 7 is enabled,

with the analog input buffers enabled. The reference precharge

buffers are disabled. The offset, gain, and phase calibration

are set to the zero position.

•

Continuous conversion mode is enabled.

SPI CONTROL FUNCTIONALITY

SPI control offers the superset of flexibility and diagnostics to

the user. The following sections highlight the functionality and

diagnostics offered when SPI control is used.

After any change to these configuration register settings, the

user must provide a sync signal to the AD7761 through either

the SPI_SYNC command, or by applying the appropriate pulse

to the START pin or SYNC_IN pin to ensure that the configuration

changes are applied correctly to the ADC and digital filters.

Channel Configuration

The AD7761 has eight fully differential analog input channels.

The channel configuration registers allow the channels to be

individually configured to adapt to the measurement required

on that channel. Channels can be enabled or disabled using the

channel standby register, Register 0x00. Analog input and

reference precharge buffers can be assigned per input terminal.

Gain, offset, and phase calibration can be controlled on a per

channel basis using the calibration registers. See the Per

Channel Calibration Gain, Offset, and Sync Phase section for

more information.

Channel Modes

In SPI control mode, the user can set up two channel modes,

Channel Mode A (Register 0x01), and Channel Mode B

(Register 0x02). Each channel mode register can have a specific

filter type and decimation ratio. Using the channel mode select

Channel Mode A or Channel Mode B, which maps that mode to

the required ADC channels. These modes allow different filter

types and decimation rates to be selected and mapped to any of the

ADC channels.

When different decimation rates are selected on different channels,

the AD7761 outputs a data ready signal at the fastest selected

decimation rate. Any channel that runs at a lower output data rate

is updated only at that slower rate. In between valid result data, the

data for that channel is set to zero and the repeated data bit is set in

the header status bits to distinguish it from a real conversion result

(see the ADC Conversion Output: Header and Data section for

more information).

On the AD7761, consider Channel Mode A as the primary group.

In this respect, it is recommended that there always be at least one

channel assigned to Channel Mode A. If all eight channels of the

AD7761 are assigned to Channel Mode B, conversion data is not

output on the data interface for any of the channels.

Table 21. Channel Mode A/Channel Mode B, Register 0x01

and Register 0x02

Bits

Bit Name

Setting

Description

Reset

Access

FILTER_TYPE_x

Filter output

0x1

Wideband filter

Sinc5 filter

[2:0]

DEC_RATE_x

Decimation rate

0x5

000 to

101

×32 to ×1024

Table 22. Channel Mode Selection, Register 0x03

Bits

Bit Name

Setting

Description

Reset

Access

[7:0]

CH_x_MODE

Channel x

0x0

Mode A

Mode B

Reset over SPI Control Interface

Two successive commands must be written to the AD7761 data

control register to initiate a full reset of the device over the SPI

interface. This action fully resets all registers to the default

conditions. Details of the commands and their sequence are

shown in Table 40.

After a reset over the SPI control interface, the AD7761 responds

to the first command sent to the device with 0x0E00. This

response, in addition to the fact that all registers have assumed

their default values, indicates that the software reset succeeded.

Sleep Mode

Sleep mode puts the AD7761 into its lowest power mode. In

sleep mode, all ADCs are disabled and a large portion of the digital

core is inactive.

The AD7761 SPI remains active and is available to the user when in

sleep mode. Write to Register 0x04, Bit 7 to exit sleep mode. For

the lowest power consumption, select the sinc5 filter before

entering sleep mode.

AD7761 Datasheet(PDF) 37 Page - Analog Devices

AD7761 Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL