AD7761 datasheet(66/76 Pages) AD

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Data Sheet

AD7761

Rev. A | Page 65 of 75

Bits

Bit Name

Settings

Description

Reset

Access

[1:0]

MCLK_DIV

MCLK division. The MCLK division bits control the divided ratio between the

MCLK applied at the input to the AD7761 and the clock used by each of the

ADC modulators. The appropriate division ratio depends on the following

factors: power mode, decimation rate, and the base MCLK available in the

system. See the Clocking, Sampling Tree, and Power Scaling section for more

information on setting MCLK_DIV correctly.

0x0

MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for low power mode.

MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.

MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.

GENERAL DEVICE CONFIGURATION REGISTER

Address: 0x05, Reset: 0x08, Name: General Configuration

Table 39. Bit Descriptions for General Configuration

Bits

Bit Name

Settings

Description

Reset

Access

CLK_QUAL_DIS

Clock qualification disable bit. Allows the user to disable

the external clock source qualification. Following a reset,

the frequency of the externally applied MCLK is checked.

It is accepted as valid if it is greater than approximately

1.15 MHz. The AD7761 then hands control over to the

external clock source. If this qualification check fails, the

NO_CLOCK_ERROR bit is set and the AD7761 continues to

run using the internal startup clock.

0x0

Users can disable this qualification check to force the

AD7761 to accept and pass control to an external clock

source with a lower frequency.

Enabled. Clock qualification check is performed.

Disabled. Clock qualification check is not performed.

RETIME_EN

SYNC_OUT signal retime enable bit.

0x0

Disabled: normal timing of SYNC_OUT.

Enabled: SYNC_OUT signal derived from alternate

MCLK edge.

VCM_PD

VCM buffer power-down.

0x0

Enabled: VCM buffer normal mode.

Powered down: VCM buffer powered down.

[1:0]

VCM_VSEL

VCM voltage. These bits select the output voltage of the

VCM pin. This voltage is derived from the AVDD1 supply

and can be output as half of that AVDD1 voltage, or other

fixed voltages, with respect to AVSS. The VCM voltage

output is associated with the Channel 0 circuitry. If

Channel 0 is put into standby mode, the VCM voltage

output is also disabled for maximum power savings.

Channel 0 must be enabled while VCM is being used

externally to the AD7761.

0x0

(AVDD1 − AVSS)/2 V.

1.65 V.

2.5 V.

2.14 V.

AD7761 Datasheet(PDF) 66 Page - Analog Devices

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