AD7761 datasheet(67/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 66 of 75

DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER

Address: 0x06, Reset: 0x80, Name: Data Control

Table 40. Bit Descriptions for Data Control

Bits

Bit Name

Settings

Description

Reset

Access

SPI_SYNC

Software synchronization of the AD7761. This command has the same

effect as sending a signal pulse to the START pin. To operate the SPI_SYNC,

the user must write to this bit two separate times. First, write a zero,

putting SPI_SYNC low, and then write a 1 to set SPI_SYNC logic high

again. The SPI_SYNC command is recognized after the last rising edge of

SCLK in the SPI instruction where the SPI_SYNC bit is changed from low to

high. The SPI_SYNC command is then output synchronous to the AD7761

MCLK on the SYNC_OUT pin. The user must connect the SYNC_OUT signal

to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed to

the SYNC_IN pins of other AD7761 devices, allowing larger channel count

simultaneous sampling systems. As per any synchronization pulse seen by

the SYNC_IN pin, the digital filters of the AD7761 are reset. The full settling

time of the filters must elapse before data is output on the data interface. In a

daisy-chained system of AD7761 devices, two successive synchronization

pulses must be applied to guarantee that all ADCs are synchronized. Two

synchronization pulses are also required in a system of more than one

AD7761 device sharing a single MCLK signal, where the DRDY pin of only

one device is used to detect new data.

0x1

Change to SPI_SYNC low.

Change to SPI_SYNC high.

SINGLE_SHOT_EN

One-shot mode. Enables one-shot mode. In one-shot mode, the AD7761

outputs a conversion result in response to a SYNC_IN rising edge.

0x0

Disabled.

Enabled.

[1:0]

SPI_RESET

Soft reset. These bits allow a full device reset over the SPI port. Two

successive commands must be received in the correct order to generate a

reset: first, write 0x03 to the soft reset bits, and then write 0x02 to the soft

reset bits. This sequence causes the digital core to reset and all registers

return to their default values. Following a soft reset, if the SPI master

sends a command to the AD7761, the device responds on the next frame

to that command with an output of 0x0E00.

0x0

No effect.

Second reset command.

First reset command.

INTERFACE CONFIGURATION REGISTER

Address: 0x07, Reset: 0x0, Name: Interface Configuration

Table 41. Bit Descriptions for Interface Configuration

Bits

Bit Name

Settings

Description

Reset

Access

[3:2]

CRC_SELECT

CRC select. These bits allow the user to implement a CRC on the data

interface. When selected, the CRC replaces the header every fourth or 16th

output sample depending on the CRC option chosen. There are two

options for the CRC; both use the same polynomial: x8 + x2 + x + 1. The

options offer the user the ability to reduce the duty cycle of the CRC

calculation by performing it less often: in the case of having it every 16th

sample, or more often in the case of every fourth conversion. The CRC is

calculated on a per channel basis and it includes conversion data only.

0x0

No CRC. Status bits with every conversion.

Replace the header with CRC message every 4 samples.

Replace the header with CRC message every 16 samples.

AD7761 Datasheet(PDF) 67 Page - Analog Devices

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