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AD7761 Datasheet(PDF) 7 Page - Analog Devices |
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AD7761 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 76 page  AD7761 Data Sheet Rev. A | Page 6 of 75 Parameter Test Conditions/Comments Min Typ Max Unit EXTERNAL REFERENCE Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − AVSS V Absolute Reference Voltage Limits2 Precharge reference buffers off AVSS − 0.05 AVDD1 + 0.05 V Precharge reference buffers on AVSS AVDD1 V Average Reference Current Fast mode Precharge reference buffers off ±72 µA/V/channel Precharge reference buffers on ±16 µA/V/channel Average Reference Current Drift Fast mode Precharge reference buffers off ±1.7 nA/V/°C Precharge reference buffers on ±49 nA/V/°C Common-Mode Rejection 95 dB DIGITAL FILTER RESPONSE Low Ripple Wideband Filter FILTER = 0 Decimation Rate Up to six selectable decimation rates 32 1024 Group Delay Latency 34/ODR sec Settling Time Complete settling 68/ODR sec Pass-Band Ripple2 ±0.005 dB Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz −0.1 dB bandwidth 0.409 × ODR Hz −3 dB bandwidth 0.433 × ODR Hz Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz Stop Band Attenuation 105 dB Sinc5 Filter FILTER = 1 Decimation Rate Up to six selectable decimation rates 32 1024 Group Delay Latency 3/ODR sec Settling Time Complete settling 7/ODR sec Pass Band −3 dB bandwidth 0.204 × ODR Hz REJECTION AC Power Supply Rejection Ratio (PSRR) VIN = 0.1 V, AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 2.5 V AVDD1 90 dB AVDD2 100 dB IOVDD 75 dB DC PSRR VIN = 1 V AVDD1 100 dB AVDD2 118 dB IOVDD 90 dB Analog Input Common-Mode Rejection Ratio (CMRR) DC VIN = 0.1 V 95 dB AC Up to 10 kHz 95 dB Crosstalk −0.5 dBFS input on adjacent channels −120 dB CLOCK See the Clock Selection section for data sheet performance functionality Crystal Frequency 8 32.768 34 MHz External Clock (MCLK) 32.768 MHz Duty Cycle 50:50 % MCLK Pulse Width2 Logic Low 12.2 ns Logic High 12.2 ns CMOS Clock Input Voltage See the Logic Inputs parameter High, VINH Low, VINL |
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