AD7761 datasheet(34/76 Pages) AD

34 / 76 page

Data Sheet

AD7761

Rev. A | Page 33 of 75

Setting the Decimation Rate

Pin control mode allows selection from four possible decimation

rates. The decimation rate is selected via the DEC1 and DEC0 pins.

The chosen decimation rate is used on all ADC channels. Table 15

shows the truth table for the DECx pins.

Table 15. Decimation Rate Control Pins Truth Table

DEC1

DEC0

Decimation Rate

×32

×64

×128

×1024

Operating Mode

The MODE3 to MODE0 pins determine the configuration of all

channels when using pin control mode. The variables controlled by

the MODEx pins are shown in Table 16. The user selects how

much current the device consumes, the sampling speed of the

ADC (power mode), how fast the ADC result is received by the

digital host (DCLK_DIV), and how the ADC conversion is

initiated (conversion operation). Figure 51 illustrates the inputs

used to configure the device in pin control mode.

Table 16. MODEx Pins: Variables for Control

Control Variable

Possible Settings

Sampling Speed/Power Consumption

Power Mode

Fast

Median

Low power

Data Clock Output Frequency (DCLK_DIV)

DCLK = MCLK/1

DCLK = MCLK/2

DCLK = MCLK/4

DCLK = MCLK/8

Conversion Operation

Standard conversion

One-shot conversion

The MODEx pins map to 16 distinct settings. The settings are

selected to optimize the use cases of the AD7761, allowing the

user to reduce the DCLK frequency for lower, less demanding

power modes and selecting either the one-shot or standard

conversion modes.

See Table 18 for the complete selection of operating modes that

are available via the MODEx pins in pin control mode.

The power mode setting automatically scales the bias currents

of the ADC and divides the applied MCLK signal to the correct

setting for that mode. Note that this is not the same as using SPI

control mode, where separate bit fields exist to control the bias

currents of the ADC and MCLK division.

In pin control mode, the modulator rate is fixed for each power

mode to achieve the best performance. Table 17 shows the

modulator division for each power mode.

Table 17. Modulator Rate, Pin Control Mode

Power Mode

Modulator Rate, fMOD

Fast

MCLK/4

Median

MCLK/8

Low power

MCLK/32

Diagnostics

Pin control mode offers a subset of diagnostics features. Internal

errors are reported in the status header output with the data

conversion results for each channel.

Internal cyclic redundancy check (CRC) errors, memory map

flipped bits, and external clocks not detected are reported by Bit

7 of the status header and indicate that a reset is required. The

status header also reports filter not settled, filter type, and filter

saturated signals. Users can determine when to ignore data by

monitoring these error flags. For more information on the status

header, see the ADC Conversion Output: Header and Data section.

PIN CONTROL MODE

PIN/SPI = LOW

OPTION TO

SELECT

BETWEEN FILTERS

TO DSP/

FPGA

CHANNEL STANDBY

CH 0 TO CH 3 STANDBY

CH 4 TO CH 7 STANDBY

OUTPUT DATA FORMAT

1 CHANNEL PER PIN

4 CHANNELS PER PIN

8 CHANNELS PER PIN

DECIMATION RATES

/32

/64

/128

/1024

MODE CONFIGURATION

MODE 0x0 TO MODE 0xF

SET UP VIA 4 PINS

DEC0/

DEC1

FILTER

DOUT7

DOUT1

DOUT0

FORMAT1

FORMAT0

ST1

AD7761

ST0

PIN/SPI

MODE0

MODE1

MODE2

MODE3

Figure 51. Pin Configurable Functions

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