AD7761 datasheet(52/76 Pages) AD

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Data Sheet

AD7761

Rev. A | Page 51 of 75

Data Interface: Standard Conversion Operation

In standard mode operation, the AD7761 operates as the master

and streams data to the DSP or FPGA. The AD7761 supplies the

data, the data clock (DCLK), and a falling edge framing signal

(DRDY) to the slave device. All of these signals are synchronous.

The data interface connections to DSP/FPGA are shown in

Figure 76. The FORMATx pins determine how the data is

output from the AD7761.

Figure 73 through Figure 75 show the data interface operating

in standard mode at the maximum data rate. In all

instances, DRDY is asserted one clock cycle before the MSB of

the data conversion is made available on the data pin.

Each DRDY falling edge starts the output of the new ADC con-

version data. The first eight bits output after the DRDY falling edge

are the header bits; the last 16 bits are the ADC conversion result.

Figure 73, Figure 74, and Figure 75 are distinct examples of the

impact of the FORMATx pins on the AD7761 output operating in

standard conversion operation.

Figure 73 to Figure 75 represent running the AD7761 at

maximum data rate for the three FORMATx options.

Figure 73 shows FORMATx = 00. Each ADC has its own data out

pin running at the MCLK/4 bit rate. In pin control mode, this is

achieved by selecting Mode 0xA (fast mode, DCLK = MCLK/4,

standard conversion, see Table 18) with the decimation rate set

as ×32.

Figure 74 shows FORMATx = 01 sharing DOUT1 at the

maximum bit rate. In pin control mode, this is achieved by

selecting Mode 0x8 (fast mode, DCLK = MCLK/1, standard

conversion) with a decimation rate of ×32.

If running in pin control mode, the example shown in Figure 75

represents Mode 0x4 (median mode, DCLK = MCLK/1,

standard conversion) with a decimation rate of ×32, giving the

maximum output data capacity possible on one DOUTx pin.

DCLK

DRDY

SAMPLE N

SAMPLE N + 1

DOUT0

DOUT1

DOUT7

Figure 73. FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate

CH0 (N)

CH1 (N)

CH2 (N)

CH3 (N)

DCLK

DRDY

DOUT0

SAMPLE N

SAMPLE N + 1

DOUT1

DOUT7

DOUT2

CH0 (N + 1)

CH1 (N + 1)

CH2 (N + 1)

CH3 (N + 1)

CH4 (N)

CH5 (N)

CH6 (N)

CH7 (N)

CH4 (N + 1)

CH5 (N + 1)

CH6 (N + 1)

CH7 (N + 1)

Figure 74. FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Maximum Data Rate

(DOUT6 and DOUT7 Are Inputs in This Configuration)

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