AD7761 datasheet(72/76 Pages) AD

72 / 76 page

Data Sheet

AD7761

Rev. A | Page 71 of 75

NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer

This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.

Table 51. Bit Descriptions for Negative Reference Precharge Buffer

Bits

Bit Name

Settings

Description

Reset

CH7_REFN_BUF

Off

0x0

CH6_REFN_BUF

Off

0x0

CH5_REFN_BUF

Off

0x0

CH4_REFN_BUF

Off

0x0

CH3_REFN_BUF

Off

0x0

CH2_REFN_BUF

Off

0x0

CH1_REFN_BUF

Off

0x0

CH0_REFN_BUF

Off

0x0

OFFSET REGISTERS

The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24 bit, signed twos complement registers for channel

offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital

output by −1/192 LSBs. For example, changing the offset register from 0 to 4800 changes the digital output by −25 LSBs. Because offset

adjustment occurs before gain adjustment, the ratio of 1/192 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a

reset or power cycle, the register values revert to the default factory setting.

Table 52. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB

Address

Name

Description

Reset

Access

MSB

Mid

LSB

MSB

Mid

LSB

0x1E

0x1F

0x20

Channel 0 offset

Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x21

0x22

0x23

Channel 1 offset

Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x24

0x25

0x26

Channel 2 offset

Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x27

0x28

0x29

Channel 3 offset

Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x2A

0x2B

0x2C

Channel 4 offset

Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x2D

0x2E

0x2F

Channel 5 offset

Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x30

0x31

0x32

Channel 6 offset

Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

0x33

0x34

0x35

Channel 7 offset

Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total)

0x00

AD7761 Datasheet(PDF) 72 Page - Analog Devices

AD7761 Datasheet(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL