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AD7761 Datasheet(PDF) 13 Page - Analog Devices |
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AD7761 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 76 page  AD7761 Data Sheet Rev. A | Page 12 of 75 Parameter Description Test Conditions/Comments Min Typ Max Unit t4 DCLK rise to DOUTx valid 2.0 ns t5 DCLK rise to DOUTx invalid −4 ns t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns t8a = DCLK = MCLK/2 tMCLK ns t8b = DCLK = MCLK/4 2 × tMCLK ns t8c = DCLK = MCLK/8 4 × tMCLK ns t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns t9a = DCLK = MCLK/2 tMCLK ns t9b = DCLK = MCLK/4 2 × tMCLK ns t9c = DCLK = MCLK/8 4 × tMCLK ns t10 MCLK rising to DCLK rising CMOS clock 37 ns t11 Setup time DOUT6 and DOUT7 14 ns t12 Hold time DOUT6 and DOUT7 0 ns t13 START low time 1 × tMCLK ns t14 MCLK to SYNC_OUT valid CMOS clock SYNC_OUT RETIME_EN bit disabled; measured from falling edge of MCLK 10 31 ns SYNC_OUT RETIME_EN bit enabled; measured from rising edge of MCLK 15 37 ns t15 SYNC_IN setup time CMOS clock 0 ns t16 SYNC_IN hold time CMOS clock 11 ns 1 These specifications are not production tested but are supported by characterization data at initial product release. Table 5. SPI Control Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit t17 SCLK period 100 ns t18 CS falling edge to SCLK rising edge 31.5 ns t19 SCLK falling edge to CS rising edge 30 ns t20 CS falling edge to data output enable 29 54 ns t21 SCLK high time 20 50 ns t22 SCLK low time 20 50 ns t23 SCLK falling edge to SDO valid 16 ns t24 SDO hold time after SCLK falling 7 ns t25 SDI setup time 0 ns t26 SDI hold time 10 ns t27 SCLK enable time 0 ns t28 SCLK disable time 0 ns t29 CS high time 10 ns t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns fMOD = MCLK/8 2.2 × tMCLK ns fMOD = MCLK/32 8.8 × tMCLK ns 1 These specifications are not production tested but are supported by characterization data at initial product release. |
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