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AD7761 Datasheet(PDF) 1 Page - Analog Devices |
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AD7761 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 76 page  8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW Data Sheet AD7761 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Precision ac and dc performance 8-channel simultaneous sampling 256 kSPS ADC ODR per channel 97.7 dB dynamic range 110.8 kHz input bandwidth (−3 dB BW) −120 dB THD, typical ±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error Optimized power dissipation vs. noise vs. input bandwidth Selectable power, speed, and input bandwidth Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel Median (half speed): 55.4 kHz BW, 27.5 mW per channel Low power (lowest power): 13.8 kHz BW, 9.375 mW per channel Input BW range: dc to 110.8 kHz Programmable input bandwidth/sampling rates CRC error checking on data interface Daisy-chaining Linear phase digital filter Low latency sinc5 filter Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz Analog input precharge buffers Power supply AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V 64-lead LQFP package, no exposed pad Temperature range: −40°C to +105°C APPLICATIONS Data acquisition systems: USB/PXI/Ethernet Instrumentation and industrial control loops Audio testing and measurement Vibration and asset condition monitoring 3-phase power quality analysis Sonar High precision medical electroencephalogram (EEG)/ electromyography (EMG)/electrocardiogram (ECG) FUNCTIONAL BLOCK DIAGRAM ADC OUTPUT DATA SERIAL INTERFACE DIGITAL FILTER ENGINE WIDEBAND LOW RIPPLE FILTER SINC5 LOW LATENCY FILTER SPI CONTROL INTERFACE 1.8V LDO SYNC_IN 1.8V LDO BUFFERED VCM VCM AIN1+ CH 1 AIN1– AIN2+ CH 2 AIN2– AIN3+ CH 3 AIN3– AIN4+ CH 4 AIN4– AIN5+ CH 5 AIN5– AIN6+ CH 6 AIN6– AIN7+ CH 7 AIN7– AIN0+ CH 0 AIN0– VCM ×8 PRECHARGE REFERENCE BUFFERS SYNC_OUT START RESET FORMAT1 FORMAT0 DRDY DCLK ST0/CS PIN/SPI ST1/SCLK DEC0/SDO DEC1/SDI AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 TO MODE0/GPIO0 FILTER/GPIO4 Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC DOUT7 AVDD1A, AVDD1B DGND AD7761 IOVDD DREGCAP REGCAPA, REGCAPB AVDD2A, AVDD2B REFx+ REFx– OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION DOUT1 DOUT0 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 P P P P P P P P P P P P P P P P ×16 ANALOG INPUT PRECHARGE BUFFERS (P) Figure 1. |
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