AD7761 datasheet(68/76 Pages) AD

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Data Sheet

AD7761

Rev. A | Page 67 of 75

Bits

Bit Name

Settings

Description

Reset

Access

[1:0]

DCLK_DIV

DCLK divider. These bits control division of the DCLK clock used to clock

out conversion data on the DOUTx pins. The DCLK signal is derived from

the MCLK signal applied to the AD7761. The DCLK divide mode allows the

user to optimize the DCLK output to fit the application. Optimizing the

DCLK signal per application depends on the requirements of the user. When

the AD7761 uses the highest capacity output on the fewest DOUTx pins, for

example, running in decimate by 32 using the DOUT0 and DOUT1 pins, the

DCLK signal must equal the MCLK signal; thus, in this case, choosing the

no division setting is the only way the user can output all the data within

the conversion period. There are other cases, however, when the ADC may

be running in fast mode with high decimation rates, or in median or low

power mode where the DCLK signal does not need to run at the same

speed as MCLK. In these cases, the DCLK divide allows the user to reduce

the clock speed and makes routing and isolating such signals easier.

0x0

Divide by 8.

Divide by 4.

Divide by 2.

No division.

DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER

Address: 0x08, Reset: 0x0, Name: BIST Control

Table 42. Bit Descriptions for BIST Control

Bits

Bit Name

Settings

Description

Reset

Access

RAM_BIST_START

RAM BIST. Filter RAM BIST is a built in self test of the internal RAM. Normal ADC

conversion is disrupted when this test is run. A synchronization pulse is required

after this test is complete to resume normal ADC operation. The test can be run at

intervals depending on user preference. The status and result of the RAM BIST is

available in the device status register; see the RAM_BIST_PASS and

RAM_BIST_RUNNING bits in Table 43.

0x0

Off.

Begin RAM BIST.

STATUS REGISTER

Address: 0x09, Reset: 0x0, Name: Device Status

Table 43. Bit Descriptions for Device Status

Bits

Bit Name

Settings

Description

Reset

Access

CHIP_ERROR

Chip error. Chip error is a global error flag that is output within the status byte

of each ADC conversion output. The following bits lead to the chip error bit

being set to logic high: CRC check on internally hard coded settings (after power-

up) does not pass; XOR check on the internal memory does not pass (this check

runs continuously in the background); and clock error is detected on power-up.

0x0

No error present.

Error has occurred.

NO_CLOCK_ERROR

External clock check. This bit indicates whether the externally applied MCLK is

detected correctly. If the MCLK is not applied correctly to the ADC at power-

up, this bit is set and the DCLK frequency is approximately 16 MHz. If this bit is set,

the chip error bit is set to logic high in the status bits of the data output

headers, and the conversion results are output as all zeros regardless of the

analog input voltages applied to the ADC channels.

0x0

MCLK detected.

No MCLK detected.

RAM_BIST_PASS

BIST pass/fail. RAM BIST result status. This bit indicates the result of the most

recent RAM BIST. The result is latched to this register and is only cleared by a

device reset.

0x0

BIST failed or not run.

BIST passed.

AD7761 Datasheet(PDF) 68 Page - Analog Devices

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