MFC2000 datasheet(351/426 Pages) ETC

351 / 426 page

Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

19-1

19. Synchronous Serial Interface (SsIF)

19.1 Introduction and Features

19.1.1 Introduction

There are two identical SSIFs in the MFC2000. The common signal and block names are used in the functional

and timing descriptions without indicating which SSIF. Two SSIFs are distinguished as SSIF1 and SSIF2 only in

the register description. The SSIF built into the MFC2000, allows system peripherals to communicate with the

MFC2000. The SSIF provides separate signals for Data (SSTXD, SSRXD), Clock (SSCLK), and optional

(SSREQ) and Data Acknowledge (SSACK). The SSIF may be configured to operate as either a master or slave

interface. After reset, SSTXD is 0 and SSSTAT is 1. The following describes the operation of this synchronous

only serial interface.

19.1.2 Features

•

Full duplex, three wire system

•

Master or slave operation (Bi-directional Clock)

•

Programmable bit rates with maximum frequency = AUXCLK/2 and minimum = AUXCLK/32 with a 50% duty

cycle.

•

Programmable clock polarity and phase

•

Internal interrupt for Receive Register Full (mask-able at the Interrupt Controller)

•

Optional data request/acknowledge interface during slave mode

•

8 data bit synchronous serial-interface with programmable data shifting order

Serial In

Ser ial O u t

Div 8

Cou n ter

Con tro l

Reg ister

Clo ck

Dr iv er &

Con tro l

Carry

Cnt = 8 , IR Q

A UXC L K

SS CL K

SS T X D

SS RX D

SSS T A T

IR Q S SIf

Data B u s

Rd/W r

R ead

Rst

Write

A ddr

Ser l C lk

Ack

Latch

Clr

Set

Wr & S lav e M o d e

Seria l C lk

Dev id er

5 b it

Figure 19-1. SSIF Block Diagram

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