MFC2000 datasheet(355/426 Pages) ETC

355 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

19-5

19.2.2 The 2nd SSIF (SSIF2)

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SSData2

01FF810B

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SSData2

01FF810A

SSData2 (7-0)

Rst. Value

xxh

Read Value

xxh

Note:

The SSData2 Register serves as Transmit Shift Register (TxBuffer2) during CPU write, or as

Receive Shift Register (RxBuffer2) during CPU read. Reading the SSData2 Register will clear

the SSInFull2 Interrupt bit. Writing to the SSData2 Register will reset the shift bit counter,

overwrite the output register and initiate an 8 bit serial shift while in serial mode.

A bit called SSSTATOut2 is added into the SSCmd2 register. The SSSTATOut2 value will be

output to the SSSTAT2/AO[2]/GPO[15] pin as the GPO[15] data when the SSSTAT2/GPO[15]

pin is programmed as GPO[15].

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SSCmd2

01FF8109

(Not Used)

SSSTATOut

Rst. Value

xxxxxxx0b

Read

Value 00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SSCmd2

01FF8108

(Not Used)

L2MSB2

SSCLKPol2

SSCLKPhas

(Not Used)

Mode12

0 - Master

1 - Slave

Rst. Value

xxx000x0b

Read

Value 00h

Bit 8:

The SSSTATOut2 bit is used only when the SSSTAT2/AO[2]/GPO[15]

pin is programmed as GPO[15]. The data value in the SSSTATOut2

bit is the GPO[15] data value.

Bit 4:

L2MSB2, Read/Write bit.

This bit controls the shifting order of the transmit and receive registers.

When the L2MSB2 bit is cleared (default), the transmit and receive

shift register will shift from the MSB to the LSB. When the L2MSB2 bit

is set, the transmit and receive register will shift from the LSB to MSB.

Bit 3:

SSCLKPol2, Read/Write bit.

This bit controls the polarity of the SSCLK2 pin. The default value is

zero. When the SSMode2 is configured at the IOMode2, the

SSCLKPol2 bit will not affect the SSCLK2 pin value.

Bit 2:

SSCLKPhas2, Read/Write bit.

The default value is zero.

MFC2000 Datasheet(PDF) 355 Page - List of Unclassifed Manufacturers

MFC2000 Datasheet(HTML) 355 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL