MFC2000 datasheet(357/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

19-7

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SSDiv2

01FF810D

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SSDiv2

01FF810C

SSInFull2

(Not Used)

SSCLK2 Divisor

Rst. Value

0xxx0000b

Read Value

00h

Bit 7:

SSInFull2, Read bit.

This bit indicates the status of the input register.

0: Empty (default)

1: Full

This bit allows the Firmware to poll the status of the serial interface

when the use of the interrupt is not desired and is cleared by reading

the in SSIF2 Data Register. SSInFull2 is active on the falling edge of

AUXCLK and is used by Interrupt controller where it masked.

Bit 6-4:

Not used

Bit 3-0:

DivReg (Divisor Register), Read/Write bits.

The Div Register is the SSCLK2 Divisor Register, which defines the

SSCLK frequency. Writing the DivReg register will cause the SSIF

logic to load the internal counter. Firmware can transmit data with the

right speed immediately after the SSCLK2 setup.

The SSCLK2 Divisor Register defines the SSCLK2 frequency, which depends on the AUXCLK frequency. The

SSCLK2 Divisor Register is a 5-bit register. The SSCLK2 frequency (fSCK)and Divisor relationship is:

TO BE ADDED

19.3 SSIF Timing

19.3.1 SSCLK Timing

When SSCLK is on (Figure 19-4), the duty cycle of SSCLK is always 50%. The SSCLK polarity is controlled by

the SSIF Command Register SSCLKPol Bit. When the SSCLKPol bit and the phase control is cleared (default),

the SSTXD signal transition is on the SSCLK falling edge. External logic can latch the SSTXD signal on the

SSCLK rising edge. When the SSCLKPol bit is set, the SSTXD signal transition is on the rising edge of the

SSCLK. External logic can latch the SSTXD signal on the SSCLK falling edge. For each write to the empty SSIF

Data Register, the SSCLK will be active for eight cycles. When there is no data on the SSTXD pin, the SSCLK will

stay in idle state, (logic zero when SSCLKPol bit is clear, and logic one when the SSCLKPol bit is set).

MFC2000 Datasheet(PDF) 357 Page - List of Unclassifed Manufacturers

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