MFC2000 datasheet(353/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

19-3

Bit 3:

SSCLKPol 1, Read/Write bit.

This bit controls the polarity of the SSCLK1 pin. The default value is

zero. When the SSMode1 is configured at the IOMode1, the

SSCLKPol1 bit will not affect the SSCLK1 pin value.

Bit 2:

SSCLKPhas1, Read/Write bit.

The default value is zero.

SSCLKPol1

SSCLKPhas1

Description (used for both master and slave modes)

Enable the external logic to clock the SSTXD1 pin on the rising edge of the SSCLK1 pin. The SSCLK1

pin’s first transition will be in the middle of the first bit.

Enable the external logic to clock the SSTXD1 pin on the falling edge of the SSCLK1 pin. The

SSCLK1 pin’s first transition will occur at the beginning of the first bit.

Enable the external logic to clock the SSTXD1 pin on the falling edge of the SSCLK1 pin. The

SSCLK1 pin’s first transition will be in the middle of the first bit.

Enable the external logic to clock the SSTXD1 pin on the rising edge of the SSCLK1 pin. The SSCLK1

pin’s first transition will occur at the beginning of the first bit.

MSB

LSB

SSCLK1

(SSCLKPol1=0,

SSCLKPhas1=0)

SSCLK1

(SSCLKPol1=0,

SSCLKPhas1=1)

SSCLK1

(SSCLKPol1=1,

SSCLKPhas1=0)

SSCLK1

(SSCLKPol1=1,

SSCLKPhas1=1)

SSTXD1

Internal strobe for

data capture(all modes)

Figure 19-2. SSCLK1 Diagram

Note: SSCLK1 is used to synchronize the movement of data both in and out of device through

SSRXD1 and SSTXD1 pins. The master and slave devices are capable of exchanging a data

byte of information during a sequence of eight clock pulses. Both master and slave devices must

be operated in the same timing mode as controlled by SSCLKPol1 and SSCLKPhas1 signals.

Bit 0:

Mode11, Read/Write bit.

This bit controls the SSIF1 master/slave modes.

0: Master (default)

1: Slave

When in the Master Mode, the SSCLK1 pin is configured as an output

pin. When in the Slave Mode, SSCLK1 signal is an input to the SSIF1.

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