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MFC2000 Datasheet(PDF) 352 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 352 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
19-2
Conexant
100723A
19.2 Register Description
19.2.1 The 1
st SSIF (SSIF1)
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
SSData1
01FF8103
(Not Used)
Rst. Value
xxh
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
SSData1
01FF8102
SSData1 (7-0)
Rst. Value
xxh
Read Value
xxh
Register Description: SSIF1 Data Register
Note:
The SSData1 Register serves as Transmit Shift Register (TxBuffer1) during CPU write, or as
Receive Shift Register (RxBuffer1) during CPU read. Reading the SSData1 Register will clear
the SSInFull1 Interrupt bit. Writing to the SSData1 Register will reset the shift bit counter,
overwrite the output register and initiate an 8 bit serial shift while in serial mode.
A bit called SSSTATOut1 is added into the SSCmd1 register. The SSSTATOut1 value will be
output to the SSSTAT1/GPIO[8] pin as the GPIO[8] data when the SSSTAT1/GPIO[8] pin is
programmed as GPIO[8] through the GPIOConfig register.
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
SSCmd1
01FF8101
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
SSSTATOut
1
Rst. Value
xxxxxxx0b
Read
Value 00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
SSCmd1
01FF8100
(Not Used)
(Not Used)
(Not Used)
L2MSB1
SSCLKPol1
SSCLKPhas
1
(Not Used)
Mode11
0 - Master
1 - Slave
Rst. Value
xxx000x0b
Read
Value 00h
Register Description: SSIF1 Command Register
Bit 8:
The SSSTATOut1 bit is used only when the SSSTAT1/GPIO[8] pin is
programmed as GPIO[8] through the GPIOConfig register. The data
value in the SSSTATOut1 bit is the GPIO[8] data value.
Bit 4:
L2MSB1, Read/Write bit.
This bit controls the shifting order of the transmit and receive registers.
When the L2MSB1 bit is cleared (default), the transmit and receive
shift register will shift from the MSB to the LSB. When the L2MSB1 bit
is set, the transmit and receive register will shift from the LSB to MSB.



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