MFC2000 datasheet(387/426 Pages) ETC

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Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

24-1

24. Countach Imaging DSP Bus Subsystem

The Countach Imaging DSP Bus Subsystem contains the Countach Imaging DSP subsystem for video/scan

image signal processing and all peripherals/memory needed for the whole operations. The main memory for

image data storage is the external DRAM/SDRAM. These peripherals are Countach Subsystem Interface, Scan

IA, Video/Scan Controller, SDRAM Controller, Video/Scan Interface, ARM Bus Interface, CDMA Controller, and

Countach Bus Unit. The Countach Imaging DSP subsystem should operate at 100 MHz or 85.7MHz. This is the

separate bus system from the ARM bus system and runs in parallel with the ARM bus system to get maximum

performance out of the MFC2000. ARM Bus Interface logic is the bridge between the ARM bus system and the

Countach Imaging DSP Bus Subsystem. Both CPU access and DMA access mastered by the ARM side are

supported to coordinate the entire system operation.

Several blocks are used to complete the connection between these peripherals:

ARM Bus Interface

connects the ARM subsystem to the internal busses.

Countach Subsystem Interface

connects the Countach core to the internal busses.

Sync. DRAM Controller

connects the external DRAM/SDRAM to the internal busses.

Video/Scan Interface

connects the Video/Scan Controller to the internal busses.

Several blocks are used for internal functions:

Countach Bus Unit

connects all internal blocks in the Countach Bus Subsystem together.

Countach DMA Controller

paces all DMA transaction between the Video/Scan Interface for video capture

and scanner, ARM Bus Interface for ARM bus system, and the Countach Subsystem Interface for the

Countach subsystem to and from the SDRAM.

Several I/O accesses on the Countach Bus Subsystem are planned:

ARM accesses the scratch pad of the Countach subsystem through ARM Bus Interface, Countach Bus Unit,

and Countach Subsystem IF.

Note: ARM will be able to access all registers in the sub-block of the Countach Bus Subsystem

through the IPB bus of the ARM bus system.

The ARM must not access the scratchpad while DMA to or from the Countach Imaging DSP

Subsystem is in progress. Failure to do so can result in corruption and/or loss of DMA data. The

ARM may access the scratchpad during all other DMA transfers, including video/scanner data to

SDRAM and SDRAM to and from ARM DRAM.

Put the DMA setting data to the Countach DMA Controller from the scratch pad of the Countach subsystem

through Countach Bus Unit, and Countach Subsystem IF after the Countach Bus Unit is informed by the GPO

signal from Countach Subsystem.

Several DMA accesses on the Countach Bus Subsystem are planned:

The DMA operation to send video and scan image data to the external SDRAM/DRAM from the Video/Scan

Controller through the Video/Scan Interface.

The DMA operation to send/receive data from/to memory on the ARM bus system through ARM Bus

Interface.

The DMA operation to send/receive data from/to the scratch pad of the Countach subsystem through

Countach Subsystem Interface.

MFC2000 Datasheet(PDF) 387 Page - List of Unclassifed Manufacturers

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