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MFC2000 Datasheet(PDF) 391 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 391 Page - List of Unclassifed Manufacturers |
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391 / 426 page  Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 24-5 Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Deferred Read Low Address (DefRdLoAddr) $01FF82AB Deferred Read Address [15] Deferred Read Address [14] Deferred Read Address [13] Deferred Read Address [12] Deferred Read Address [11] Deferred Read Address [10] Deferred Read Address [9] Deferred Read Address [8] Rst. Value 00h Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Deferred Read Low Address (DefRdLoAddr) $01FF82AA Deferred Read Address [7] Deferred Read Address [6] Deferred Read Address [5] Deferred Read Address [4] Deferred Read Address [3] Deferred Read Address [2] Deferred Read Address [1] Deferred Read Address [0] Rst Value 00h Read Value 00h Bit 15-0 Deferred Read Address [15:0] These sixteen bits, in conjunction with the seven bits of the Deferred Read High Address register, make up the deferred read address. It is a halfword address, not a byte address. Notes: 1. The deferred read address is a halfword address in the Countach Bus Subsystem address space. Countach DRAM address space is $000000–$3FFFFF and Countach Subsystem scratch pad address space is $400000–$4001FF. 2. Writing this register begins the deferred access operation. This register must be the last one written when initiating a deferred read access. 3. During a deferred read access, all deferred registers are locked out from ARM writes. 4. When the deferred read access completes, an interrupt is generated via the Countach DMA Done bit in the ARM Bus Interface Interrupt Status register. Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Deferred Write High Address (DefWrHiAddr) $01FF82AD (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst. Value xxh Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Deferred Write High Address (DefWrHiAddr) $01FF82AC (Not Used) Deferred Write Address [22] Deferred Write Address [21] Deferred Write Address [20] Deferred Write Address [19] Deferred Write Address [18] Deferred Write Address [17] Deferred Write Address [16] Rst Value x0000000b Read Value 00h Bit 15-7 Not used Bit 6-0 Deferred Write Address [22:16] These seven bits, in conjunction with the sixteen bits of the Deferred Write Low Address register, make up the deferred write address. It is a halfword address, not a byte address. |
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