MFC2000 datasheet(394/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-8

Conexant

100723A

24.3 ARM BUS INTERFACE

24.3.1 Function Description

The Arm Bus interface block attaches the Countach Bus Subsystem to the ARM Bus System. The ARM can

directly access the various registers of the Countach Bus Subsystem. It can access the Countach Bus

Subsystem’s SDRAM and the Countach Imaging DSP subsystem’s scratch pad memory and the SDRAM with

discrete I/O accesses with some wait state penalty. It can also access the SDRAM via DMA accesses. To

accommodate the ARM DMA interchange, two channels are provided: one for transfers into the SDRAM and one

for transfers out of the SDRAM.

In addition, two handshaking signals are provided for interrupting of each processor and allow the ARM to

interrupt the Countach core. It is implemented through a register in the Countach Subsystem Interface. The

arm_attn signal comes directly from the Countach core and is an input to the ARM interrupt controller.

24.3.2 Register Description

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

ARM Bus Interface

Interrupt Status

(ABIIrqStat)

$01FF8283

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

ARM Bus Interface

Interrupt Status

(ABIIrqStat)

$01FF8282

(Not Used)

Countach

Subsystem

Interrupt

VSI

Overrrun

Deferred

Access

Done

C2A DMA

Done

Countach

DMA Done

Video/

Scan DMA

Done

Rst Value

xx000000b

Read Value

00h

Bit 15-6

Not used

Bit 5

Countach Subsystem Interrupt

Countach Subsystem has interrupted the ARM either in IRQP or

IRQP2, depending on the setting of the Countach Interrupt Source bit

of the ABICountachCtrl register.

Bit 4

VSI Overrun

The second VSI ping-pong buffer has been filled before the first has

been emptied, resulting in loss of data.

Bit 3

Deferred Access Done

A deferred access to/from scratch pad or SDRAM has completed. If a

deferred read was requested, the data in the Deferred Read Access

Data register is now valid.

Bit 2

C2A DMA Done

C2A (SDRAM to Arm Bus System) block size has been reached.

Bit 1

Countach DMA Done

DMA operation specified by Countach scratch pad parameters has

completed.

Bit 0

Video/Scan DMA Done

Two-dimensional DMA from Video/Scan Interface to SDRAM has

completed (two fields) or one scan line has completed.

Note: Each of these bits are cleared by writing it to a one. This allows individual interrupts to be

cleared without affecting the others.

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