MFC2000 datasheet(398/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-12

Conexant

100723A

24.5 COUNTACH DMA CONTROLLER

24.5.1 Function Description

This block handles data transfers between several of the blocks of the Countach subsystem.

It has three potential bus masters: the Video/Scan Interface, the Arm Bus interface, and the Countach subsystem.

The VDMA employs a hierarchical round-robin arbitration scheme, with the Video/Scan Interface block at the

highest priority and the Countach subsystem and Arm Bus interface in a round-robin scheme at the lowest

priority. A round-robin arbitration scheme is one in which no requestor can be serviced until all other requestors at

the same priority have been serviced if they are also requesting. A hierarchical arbitration scheme is one in which

if a higher priority group is requesting service it is given priority over a lower priority group, after which the lower

priority group is handled in its predetermined manner.

Below is a table of the four DMA channels, their functionality, and priorities.

Table 24-2. DMA Channels: Functionality and Priorities

Chan

Usage

−−

⇒

Priority

Description

0VSI

A-1

Scan/video data to (S)DRAM

CSI I/O

B-1

Countach scratch pad data to/from (S)DRAM

2ABI in

B-2

ARM data to (S)DRAM

ABI out

B-3

ARM data from (S)DRAM

Legend:

Chan

DMA channel

VSI

Video/Scanner Interface

CSI

Countach Subsystem Interface

ABI

ARM Bus Interface

Incrementing address

−−

Decrementing address

Address Jumping at boundaries.

⇒

Burst cycles

Throttle: Limits number of DMA Cycles per CBSS clocks

Block limit

Notes:

(1)

To be supplied.

Channels 0,2, and 3 operate in a similar fashion as existing channels in the ARM DMA logic. These channels are

programmed by ARM-accessible registers and contain address registers and, for channel 3, a block limit and

enable register.

Channel 1 is very different in its operation. It contains no ARM-accessible registers. It is controlled by the

Countach Subsystem. However, since the Countach Subsystem cannot be a bus master and program the

registers directly, the Countach DMA logic must fetch the register values from the Countach Subsystem scratch

pad.

The Countach Subsystem has no DMA handshaking signals as it is able to accept data at a fixed rate. DMA data

is transferred to and from the Countach Subsystem via the scratch pad at fixed addresses. Thus, it appears as

memory (SDRAM) to I/O (scratch pad) transfers.

Channel 1 is shared by five logical DMA channels within the Countach Subsystem, but they operate

consecutively, not concurrently (i.e., DMA for one logical channel is completely before DMA for another logical

channel is begun. Finally, logical DMA channel 4 (of physical DMA channel 1) is used for program DMA. Because

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