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MFC2000 Datasheet(PDF) 401 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 401 Page - List of Unclassifed Manufacturers |
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401 / 426 page ![]() Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 24-15 Bit 15-0 Block size in halfwords Block size = Block Size Register + 1. If this parameter is zero, the channel should be considered improperly configured and not enabled. Also, no further parameters need to be fetched in this circumstance. This register programs the data block size (number of DMA accesses) between address steps, AST. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Number of sub ranges (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Number of sub ranges (7:0) Parameter Description: NSR parameter (Refer to the above diagram) Bit 15-0 Number of sub ranges Total number of sub ranges = register value + 1; When this register is set to $0000, one block will be transferred before the IRQ occurs. This register controls the number of number of sub ranges (NSR), or address steps that occur in the complete DMA transfer. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Address step between sub ranges (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address step between sub ranges (7:0) Parameter Description: AST parameter (Refer to the above diagram) Bit 15-0 Address step between sub ranges This parameter should only be fetched if the Enable channel bit of the BAH parameter is high. This register controls the address step size between data blocks. The register value is added to the last DMA address accessed in a block plus 1. |
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