MFC2000 datasheet(399/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

24-13

Countach instructions are 40 bits wide, they must be transferred in sections. This is accomplished by DMA

transfers to three consecutive scratch pad addresses.

Each of the five logical channels is started by the Countach Subsystem by a high-going pulse on the Countach

GPIO signal sp_gpio[0]. When the pulse is detected, the Countach DMA Controller fetches the parameters from

the scratch pad, executes the desired DMA operation, and interrupts the Countach Subsystem at the completion.

The scratch pad addresses for the various DMA parameters are shown below:

Table 24-3. DMA Parameters Scratch Pad Addresses

Scratch pad

address

Parameter

Countach Subsystem DMA Channel Parameters

0xF9

ENB – Enables the DMA operation

0xFA

BAH – most significant bits of base address and DMA control bits

0xFB

BAL – least significant bits of base address

0xFC

SZ – number of halfwords to transfer

0xFD

NSR – number of sub ranges

0xFE

AST – address step between sub ranges

Scratch pad

address

Function

0x100

Countach Subsystem DMA channel 0 data port

0x101

Countach Subsystem DMA channel 1 data port

0x102

Countach Subsystem DMA channel 2 data port

0x103

Countach Subsystem DMA channel 3 data port

0x1B0

Countach Subsystem DMA channel 4 program data port (bits 15:0)

0x1B1

Countach Subsystem DMA channel 4 program data port (bits 31:16)

0x1B2

Countach Subsystem DMA channel 4 program data port (bits 39:32)

To program and initiate a DMA transfer, firmware must first setup the parameter registers shown above. The

process of reading the ENB register will cause hardware to generate either an ARM IRQ or start a DMA transfer.

If the LSB of the ENB Register is 1 an ARM IRQ is generated. If the value of the LSB is 0, a DMA transfer is

initiated.

Sub Range Value

Block Size

Memory

This diagram depicts how the SZ, NSR and AST register all work together. The block size is controlled by the SZ

the last DMA address + one is added to the AST register, and is used as the starting address for the next block.

This process continues for the number of cycles specified by the NSR register. Once the NSR value is met, an

IRQ is generated.

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