MFC2000 datasheet(397/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

24-11

ARM access to the ABI buffers are provided for diagnostic purposes only and should not be used as part of

normal operation.

When the ARM makes an access to these buffers, the ARM is held off and clock domain synchronization occurs

before the access is completed. As a result, a significant wait state penalty is incurred. This penalty will be even

longer if a local DMA operation is in progress when the access is made as the ARM is held off for both the clock

domain synchronization and the completion of the local DMA transfer.

There is a risk of data corruption when the ARM makes write accesses to these buffers while a DMA transfer is in

progress. This can occur because the buffers alternate betweeen a DMA transfer sequence in the ARM Bus

Subsystem domain and a DMA transfer sequence in the Countach Bus Subsystem domain. If the write operation

occurs between these DMA transfers, the DMA data in the buffer will be replaced with the ARM data.

24.4 Countach Imaging DSP Subsystem Interface

ARM as either bytes or halfwords.

The buffer is located at the following addresses:

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Countach DMA

Buffer

(CSIDmaBuf)

$01FF830x

CSI Buffer

Data [15]

CSI Buffer

Data [14]

CSI Buffer

Data [13]

CSI Buffer

Data [12]

CSI Buffer

Data [11]

CSI Buffer

Data [10]

CSI Buffer

Data [9]

CSI Buffer

Data [8]

Rst. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Countach DMA

Buffer

(CSIDmaBuf)

$01FF830x

CSI Buffer

Data [7]

CSI Buffer

Data [6]

CSI Buffer

Data [5]

CSI Buffer

Data [4]

CSI Buffer

Data [3]

CSI Buffer

Data [2]

CSI Buffer

Data [1]

CSI Buffer

Data [0]

Rst Value

00h

Read Value

00h

Table 24-1. Needs a title

$01FF8300-01

CSI DMA Buffer halfword 0

$01FF8302-03

CSI DMA Buffer halfword 1

$01FF8304-05

CSI DMA Buffer halfword 2

$01FF8306-07

CSI DMA Buffer halfword 3

$01FF8306-07

CSI DMA Buffer halfword 4

$01FF8306-07

CSI DMA Buffer halfword 5

$01FF8306-07

CSI DMA Buffer halfword 6

$01FF8306-07

CSI DMA Buffer halfword 7

ARM access to the CSI buffers are provided for diagnostic purposes only and should not be used as part of

normal operation.

When the ARM makes an access to these buffers, the ARM is held off and clock domain synchronization occurs

before the access is completed. As a result, a significant wait state penalty is incurred. This penalty will be even

longer if a local DMA operation is in progress when the access is made as the ARM is held off for both the clock

domain synchronization and the completion of the local DMA transfer.

There is a risk of data corruption when the ARM makes write accesses to this buffer while a DMA transfer is in

progress. It is also possible that an access to this buffer can cause spurious writes to the scratchpad space while

a DMA transfer is in progress.

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