MFC2000 datasheet(395/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

24-9

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

ARM Bus Interface

Interrupt Enable

(ABIIrqEnable)

$01FF8285

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

ARM Bus Interface

Interrupt Enable

(ABIIrqEnable)

$01FF8284

(Not Used)

Countach

Interrupt

Enable

VSI

Overrrun

Interrupt

Enable

Deferred

Access

Interrupt

Enable

C2A DMA

Interrupt

Enable

Countach

DMA

Interrupt

Enable

Video/ Scan

DMA

Interrupt

Enable

Rst Value

xx000000b

Read Value

00h

Bit 15-6

Not used

Bit 5

Countach Interrupt Enable

Enables interrupt when the Countach has interrupted the ARM Bus via

the IRQP or IRQP2 signals.

Bit 4

VSI Overrun Interrupt Enable

Enables interrupt when the second VSI ping-pong buffer has been

filled before the first has been emptied, indicating in loss of data.

Bit 3

Deferred Access Interrupt Enable

Enables interrupt when a deferred access to/from scratch pad or

SDRAM has completed.

Bit 2

C2A DMA Interrupt Enable

Enables interrupt when C2A (SDRAM to Arm Bus System) block size

has been reached.

Bit 1

Countach DMA Interrupt Enable

Enables interrupt when DMA operation specified by Countach scratch

pad parameters has completed.

Bit 0

Video/Scan DMA Interrupt

Enables interrupt when two-dimensional DMA from Video/Scan

Interface to SDRAM has completed (two fields) or one scan line has

been completed.

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

ARM Bus Interface

Countach Control (W)

(ABICountachCtrl)

$01FF8287

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

ARM Bus Interface

Countach Control (W)

(ABICountachCtrl)

$01FF8286

(Not Used)

Countach

Interrupt

Source

Reset

Countach

Bus

Subsystem

(W)

Start

Countach

DMA (W)

Abort

Countach

DMA (W)

Reset

Countach

Subsystem

(W)

Interrupt

Countach

Subsystem

(W)

Rst Value

xxxx0000b

Read Value

00h

Bit 15-6

Not used

Bit 5

Countach Interrupt Source

This bit selects which interrupt output from the Countach DSP

Subsystem is used to interrupt the ARM via the Countach Interrupt bit

in the ARM Bus Interface Interrupt Status Register. A value of 0

selects the IRQP signal and a value of 1 selects the IRQP2 signal.

Bit 4

Reset Countach Bus Subsystem

Writing a one to this bit resets the entire Countach Bus Subsystem

(CBSS.)

MFC2000 Datasheet(PDF) 395 Page - List of Unclassifed Manufacturers

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