MFC2000 datasheet(390/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-4

Conexant

100723A

24.2 COUNTACH IMAGING DSP BUS UNIT

24.2.1 Function Description

The Countach Bus Unit is the conduit for all data and address between the various block of the Countach Bus

System. It also decides which blocks become master of these busses.

There are four busses in the Countach Bus System:

•

CPB

address and data to and from the Countach Subsystem Interface

•

DPB

address and data to and from the Synchronous DRAM Interface

•

IPB

address and data to and from the ARM Bus Interface

•

VPB

data from the Video/Scan Interface

Because of these separate busses (as opposed to a single tri-state muxed bus), it is possible to have multiple bus

masters. The possible connections between these busses are:

•

IPB

↔ CPB, VPB ↔ DPB: ARM Bus Interface makes discrete I/O accesses to Countach Subsystem scratch

pad while Video/Scan Interface makes DMA accesses to Synchronous DRAM Interface.

•

CPB

↔ DPB: Countach Subsystem Interface makes DMA accesses to Synchronous DRAM Interface.

•

IPB

↔ DPB, {Countach DMA Controller} ↔ cpb: ARM Bus Interface makes either discrete I/O accesses or

DMA accesses to Synchronous DRAM Interface while Countach DMA Controller fetches DMA parameters

from Countach Subsystem scratch pad.

24.2.2 Register Description

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Deferred Read High

Address

(DefRdHiAddr)

$01FF82A9

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Deferred Read High

Address

(DefRdHiAddr)

$01FF82A8

(Not Used)

Deferred

Read

Address [22]

Deferred

Read

Address [21]

Deferred

Read

Address [20]

Deferred

Read

Address [19]

Deferred

Read

Address [18]

Deferred

Read

Address [17]

Deferred

Read

Address [16]

Rst Value

x0000000b

Read Value

00h

Bit 15-7

Not used

Bit 6-0

Deferred Read Address [22:16] These seven bits, in conjunction with the sixteen bits of the Deferred

Read Low Address register, make up the deferred read address. It is a

halfword address, not a byte address.

MFC2000 Datasheet(PDF) 390 Page - List of Unclassifed Manufacturers

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