LP87332D datasheet(17/74 Pages) TI1

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LP87332D

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SNVSAU6 – NOVEMBER 2017

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Feature Description (continued)

7.3.1.4 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband

frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add

EMI-filters and shields to the boards. The LP87332D has register selectable spread-spectrum mode which

minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency

varies around the center frequency, reducing the EMI emissions radiated by the converter and associated

passive components and PCB traces (see Figure 7). This feature is available only when internal RC oscillator is

used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in CONFIG

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread

spectrum architecture of the LP87332D spreads that energy over a large bandwidth.

Figure 7. Spread-Spectrum Modulation

7.3.2 Sync Clock Functionality

The LP87332D device contains a CLKIN input to synchronize the switching clock of the buck regulators with the

external clock. The block diagram of the clocking and PLL module is shown in Figure 8. Depending on the

EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt

is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1

limits (–30%/+10%) of the selected frequency for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is

expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1

and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.

LP87332D Datasheet(PDF) 17 Page - Texas Instruments