LP87332D datasheet(27/74 Pages) TI1

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V(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGOOD pin

EN pin

VOUT (Buck1)

VOUT (LDO0)

Buck1 internal powergood

LDO0 internal powergood

Active

800us Timer

Buck internal enable

800us Timer

LDO0 internal enable

4ms

2ms

Clear fault

LP87332D

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SNVSAU6 – NOVEMBER 2017

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Figure 13. PGOOD Pin Operation in Gated Mode

7.3.8.1.2

PGOOD Pin Continuous Mode

The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in

PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration.

•

PGOOD is set to inactive or de-asserted as soon as regulator is enabled.

•

PGOOD status begins indicating output voltage regulation status immediately and continuously.

•

During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de-

asserted while output voltages are outside of regulation ranges and active or asserted when inside of

regulation ranges.

The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing

1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are

cleared by clearing the interrupt bits.

When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.

When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the

invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows

all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 14

and an example of operation is shown in Figure 15.

The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs

are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is

selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.

LP87332D Datasheet(PDF) 27 Page - Texas Instruments

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