CS5530A datasheet(101/259 Pages) AMD

101 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

101

PC/AT Compatibility Logic

Revision 1.1

Of the 16 IRQs, four are mapped as shown in Table 4-43,

leaving 12 external interrupts. The two controllers are cas-

caded through IRQ2. The internal 8254 PIT connects to

IRQ0. The real-time clock interface chip (see Figure 4-18

"External RTC Interface" on page 109) and the external

coprocessor interface (see Figure 4-1 "Processor Signal

Connections" on page 48) connect to IRQ8# and IRQ13

respectively.

The CS5530A allows the PCI interrupt signals INTA#-

INTD# (also known in industry terms as PIRQx#) to be

routed internally to any IRQ signal. The routing can be

modified through the CS5530A’s configuration registers. If

this is done, the IRQ input must be configured to be level-

rather than edge-sensitive. IRQ inputs may be individually

programmed to be active low, level-sensitive with the Inter-

rupt Sensitivity configuration registers at I/O address space

4D0h and 4D1h. PCI interrupt configuration is discussed in

further detail in Section 4.5.4.4 "PCI Compatible Interrupts"

on page 103.

PIC Interrupt Sequence

A typical AT-compatible interrupt sequence is as follows.

Any unmasked interrupt generates the INTR signal to the

CPU. The interrupt controller then responds to the interrupt

acknowledge (INTA) cycles from the CPU. On the first INTA

cycle the cascading priority is resolved to determine which

of the two 8259 controllers output the interrupt vector onto

the data bus. On the second INTA cycle the appropriate

8259 controller drives the data bus with the correct inter-

rupt vector for the highest priority interrupt.

By default, the CS5530A responds to PCI INTA cycles

because the system interrupt controller is located within the

CS5530A. This may be disabled with F0 Index 40h[7] (see

Table 4-44). When the CS5530A responds to a PCI INTA

cycle, it holds the PCI bus and internally generates the two

INTA cycles to obtain the correct interrupt vector. It then

asserts TRDY# and returns the interrupt vector.

PIC I/O Registers

Each PIC contains registers located in the standard I/O

address locations, as shown in Table 5-30 "Programmable

Interrupt Controller Registers" on page 220.

An initialization sequence must be followed to program the

interrupt controllers. The sequence is started by writing Ini-

tialization Command Word 1 (ICW1). After ICW1 has been

written, the controller expects the next writes to follow in

the sequence ICW2, ICW3, and ICW4 if it is needed. The

Operation Control Words (OCW) can be written after initial-

ization. The PIC must be programmed before operation

begins.

Since the controllers are operating in cascade mode, ICW3

of the master controller should be programmed with a

value indicating that IRQ2 input of the master interrupt con-

troller is connected to the slave interrupt controller rather

than an I/O device as part of the system initialization code.

In addition, ICW3 of the slave interrupt controller should be

programmed with the value 02h (slave ID) and corresponds

to the input on the master controller.

Table 4-43. PIC Interrupt Mapping

Master IRQ#

Mapping

IRQ0

Connected to the OUT0 (system timer) of

the internal 8254 PIT.

IRQ2

Connected to the slave’s INTR for a

cascaded configuration.

IRQ8#

Connected to external real-time clock.

IRQ13

Connected to the coprocessor interface.

IRQ[15:14, 12:9,

7:3, 1]

External interrupts.

Table 4-44. PCI INTA Cycle Disable/Enable Bit

Bit

Description

F0 Index 40h

PCI Function Control Register 1 (R/W)

Reset Value = 89h

PCI Interrupt Acknowledge Cycle Response: Allow the CS5530A responds to PCI interrupt acknowledge cycles.

0 = Disable; 1 = Enable.

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