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CS5530A Datasheet(PDF) 103 Page - Advanced Micro Devices |
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CS5530A Datasheet(HTML) 103 Page - Advanced Micro Devices |
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103 / 259 page  AMD Geode™ CS5530A Companion Device Data Book 103 PC/AT Compatibility Logic Revision 1.1 4.5.4.4 PCI Compatible Interrupts The CS5530A allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also known in industry terms as PIRQx#) to be mapped internally to any IRQ signal with the PCI Interrupt Steering Registers 1 and 2, F0 Index 5Ch and 5Dh (Table 4-46). This reassignment does not disable the corresponding IRQ pin. Two interrupt signals may not be assigned to the same IRQ. PCI interrupts are low-level sensitive, whereas PC/AT inter- rupts are positive-edge sensitive; therefore, the PCI inter- rupts are inverted before being connected to the 8259. Although the controllers default to the PC/AT-compatible mode (positive-edge sensitive), each IRQ may be individu- ally programmed to be edge or level sensitive using the Interrupt Edge/Level Sensitivity registers in I/O Port 4D0h and 4D1h, as shown in Table 4-47. However, if the control- lers are programmed to be level-sensitive via ICW1, all interrupts must be level-sensitive. Figure 4-16 shows the PCI interrupt mapping for the master/slave 8259 interrupt controller. Figure 4-16. PCI and IRQ Interrupt Mapping PCI INTA#-INTD# IRQ[15:14,12:9,7:3,1] Steering Registers F0 Index 5Ch,5Dh ICW1 4D0h/4D1h 16 1 12 12 4 MASTER/SLAVE 8259 PIC INTR IRQ[13,8,0] 3 Level/Edge IRQ3 IRQ4 IRQ15 Sensitivity Table 4-46. PCI Interrupt Steering Registers Bit Description F0 Index 5Ch PCI Interrupt Steering Register 1 (R/W) Reset Value = 00h 7:4 INTB# Target Interrupt: Selects target interrupt for INTB#. 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTA# Target Interrupt: Selects target interrupt for INTA#. 0000 = Disable 0100 = IRQ4 1000 = RSVD ‘ 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. F0 Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value = 00h 7:4 INTD# Target Interrupt: Selects target interrupt for INTD#. 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTC# Target Interrupt: Selects target interrupt for INTC#. 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. |
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