CS5530A datasheet(139/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

139

Display Subsystem Extensions

Revision 1.1

4.8.5

Display Interface

The CS5530A interfaces directly to a variety of display

devices including conventional analog CRT displays, TFT

flat panels, or optionally to digital NTSC/PAL encoder

devices.

4.8.5.1

Video DACs

The CS5530A incorporates three 8-bit video Digital-to-Ana-

log Converters (DACs) for interfacing directly to CRT dis-

plays. The video DACs meet the VESA specification and

are capable of operation up to 157.5 MHz for supporting up

to 1280x1024 display at a 85 Hz refresh rate and are VESA

compliant.

4.8.5.2

VESA DDC2B / DPMS

The CS5530A supports the VESA DDC2B and DPMS

standards for enhanced monitor communications and

power management support.

4.8.5.3

Flat Panel Support

The CS5530A also interfaces directly to industry standard

18-bit Active Matrix Thin-Film-Transistor (TFT) flat panels.

The CS5530A includes 24-bit to 18-bit dithering logic to

increase the apparent number of colors displayed on 18-bit

flat panels.

In addition, the CS5530A incorporates power sequencing

logic to simplify the design of a portable system.

If flat panel support is not required, the flat panel output

port may be used to supply digital video data to one of sev-

eral types of NTSC/PAL encoder devices on the market.

Flat Panel Power-Up/Down Sequence

When the Flat Panel Power Enable bit (F4BAR+Memory

Offset 04h[6]) transitions from a 0 to 1, the FP_ENA_VDD

signal is enabled. This is followed by the data bus (includ-

ing syncs and ENA_DISP). Finally, FP_ENA_BKL is

enabled. The time between each of these successive

stages is set by the value of the Power Sequence Delay

bits (F4BAR+Memory Offset 04h[19:17]). The value in

these bits refer to the number of graphics frames that will

elapse between each successive enabling of the TFT sig-

nals. For example, if the Power Sequence Delay is set to 3h

(011b), then three frame times will elapse between the time

when FP_ENA_VDD is transitioned and the data bus is

transitioned. Likewise, three frame times will elapse

between

the

data

bus

getting

enabled

and

the

FP_ENA_BKL is transitioned. If the panel is being

refreshed at 100 Hz, each frame lasts 1 ms. So, if the

Power Sequence Delay is set to 3, 3 ms will elapse

between transitions. When powering off the panel, the sig-

nals are transitioned in the opposite order (FP_ENA_BKL,

data bus, FP_ENA_VDD) using the same Power Sequence

Delay in the power-down sequence.

DAC Blank Enable: This bit enables the blank to the video DACs.

0 = DACs are constantly blanked; 1 = DACs are blanked normally.

CRT Vertical Sync Enable: Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable.

CRT Horizontal Sync Enable: Enables the CRT horizontal sync. Used for VESA DPMS support.

0 = Disable; 1 = Enable.

Display Enable: Enables the graphics display pipeline. It is used as a reset for the display control logic.

0 = Reset display control logic; 1 = Enable display control logic.

Table 4-76. Display Configuration Register (Continued)

Bit

Description

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