IC-PI datasheet(19/49 Pages) ICHAUS

19 / 49 page

preliminary

iC-PI PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev B1, Page 19/48

If an EEPROM is connected and iC-PI is enabled for

error logging (refer to description on page 39), the error

memory needs to be cleared afterwards.

Addr 0x02

bit 7 = 0

Write Registers

0x00 ... 0x2F

Addr 0x02

bit 7 = 1

RUN = 0

RUN = 1

Configuration

Write Check Sum

0x2F

Confirmation

Clear E2Prom Errors

0x31-0x33

Reset of Error

Memory

Figure 8: Programming via I2C. RUN is altered by

changing only bit 7 of address 0x02 and

leaving bits 6:0 unchanged.

Note: iC-PI verifies its RAM contents cyclically ver-

sus the checksum stored at address 0x2F. As these

check cycles take less than half a millisecond, writing

a single byte or parameter can trigger a configura-

tion error, at least temporarily, until the checksum has

been updated.

Note: When finally clearing the error memory, the

sensor system should run properly as otherwise iC-PI

may update the error memory immediately (if error

logging is enabled).

Identification of Chip Release

For chip release verification purposes an identification

value is stored at address 0x3F; writing to this ROM

address is not permitted.

CHPREL

Addr. 0x3F, bit 7:0 (ROM)

Code

Chip Release

0x34

iC-PI Y

0x35

iC-PI Y1

0x36

iC-PI X

Table 10: Chip Release

Access Rights

Read access in I2C slave mode (ENSL = 1)

RAM Addr.

Content

0x00-0x2F

Configuration data

(see EEPROM addresses 0x00-0x2F)

0x30-0x33

Error data

(see EEPROM addresses 0x30-0x33)

0x34-0x37

Position data

0x38-0x3E

Not available

0x3F

Chip release CHPREL(7:0)

0x40-0x7F

Not available

Table 11: RAM Read Access

The internally available absolute angle information can

be accessed by reading addresses 0x34 and 0x35.

Each time address 0x34 is read the internal position

data is latched.

Write access in I2C slave mode (ENSL = 1)

RAM Addr.

Access and conditions

0x00-0x1C

Changes permitted, no restrictions

0x1D-0x25

Changes permitted during standby (RUN = 0)

0x26-0x2F

Changes permitted, no restrictions

0x30-0x33

Changes permitted, no restrictions

0x34-0x35

No write access permitted

0x36

Write access impacts bit 7 (PMODE) only.

0x37-0x3F

No write access permitted

Table 12: RAM Write Access

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