IC-PI datasheet(36/49 Pages) ICHAUS

36 / 49 page

preliminary

iC-PI PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev B1, Page 36/48

OUTPUT SETTINGS AND ZERO SIGNAL

The interpolation factor (IPF) determines the number

of A/B signal cycles per input signal period. These A/B

signal cycles are counted internally by register POS, to

allow an adjustable gating with the external index signal

applied to the zero inputs.

POS starts from zero (when the sine/cosine input phase

is zero degrees) and reaches POSmax = IPF - 1 as its

maximum. The internal A/B signal cycle adheres to the

following pattern:

A 1 1 0 0

B 1 0 0 1

Table 53: Internal A/B Signal Cycle

Inversions and reversals can be selected for the output

of the A/B/Z signals using CFGABZ(7:4), and the zero

signal can be gated with any combination of the internal

A and B signal using CFGABZ(3:0).

CFGABZ

Addr. 0x1D, bit 7:0

Bit

Function and Description

Output inversion for channel A: PA<>NA

PA = P1i xor CFGABZ(7)

Output inversion for channel B: PB<>NB

PB = P2i xor CFGABZ(6)

Output inversion for index channel: PZ<>NZ

PZ = P0i xor CFGABZ(5)

Exchange of the A/B signals

0: P1i = A, P2i = B

1: P1i = B, P2i = A

Zero Signal Gating CFGABZ(3:0)

Enable for A = 1, B = 1

Enable for A = 1, B = 0

Enable for A = 0, B = 0

Enable for A = 0, B = 1

Table 54: Output Logic

Figure 20: Signal path from A and B to PA/NA and

PB/NB

Zero Signal Generation

The zero signal generation depends on the internal

window signal ZIn which is derived from a comparator

evaluating the calibrated input signals of CH0.

As the width of the window signal ZIn varies with the

offset calibration of CH0, its correct size and posi-

tion should be checked ahead of configuring any gat-

ing. Using Mode ABZ, the internal window signal

ZIn can be output to pin ERR for inspection (requires

EMASKA = 0x010 and EMTD = 0x0).

Figure 21: Signal path from ZIn to PZ/NZ

The zero signal output to PZ is generated during the

A/B cycle where the POS number is equal to CFGZ-

POS. It is therefore essential that this specific A/B cycle

is fully enclosed by the window signal ZIn.

CFGZPOS

Addr. 0x1E, bit 7:0

Bit

Description

1: Masking enabled

0: Masking disabled

(6:0)

Selection of A/B cycle number:

IPF < 200: POS = CFGZPOS(6:0)

IPF ≥ 200: POS = 8 * CFGZPOS(6:0)

Table 55: Zero Signal Positioning

Note: The A/B cycle number configured by CFGZ-

POS must not exceed POSmax = IPF - 1.

So when changing the interpolation factor IPF, CFGZ-

POS must be adapted accordingly.

ENZFF

Addr. 0x02, bit 4

Code

Description

Zero signal output with state change of P0i

Zero signal output synchronized with A/B signal

Table 56: Zero Signal Synchronization

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