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BMA255

Data sheet

Page 18

BST-BMA255-DS004-05 | Revision 1.2 | August 2014

Bosch Sensortec

third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.

Note: Specifications within this document are subject to change without notice.

4.3 Sensor data

4.3.1 Acceleration data

The width of acceleration data is 12 bits given in two´s complement representation. The 12 bits

for each axis are split into an MSB upper part (one byte containing bits 11 to 4) and an LSB

lower part (one byte containing bits 3 to 0 of acceleration and a (0x02, 0x04, 0x06) new_data

flag). Reading the acceleration data registers shall always start with the LSB part. In order to

ensure the integrity of the acceleration data, the content of an MSB register is locked by reading

the corresponding LSB register (shadowing procedure). When shadowing is enabled, the MSB

must always be read in order to remove the data lock. The shadowing procedure can be

disabled (enabled) by writing ´1´ (´0´) to the bit shadow_dis. With shadowing disabled, the

content of both MSB and LSB registers is updated by a new value immediately. Unused bits of

the LSB registers may have any value and should be ignored. The (0x02, 0x04, 0x06)

new_data flag of each LSB register is set if the data registers have been updated. The flag is

reset if either the corresponding MSB or LSB part is read.

Two different streams of acceleration data are available, unfiltered and filtered. The unfiltered

data is sampled with 2kHz. The sampling rate of the filtered data depends on the selected filter

bandwidth and is always twice the selected bandwidth (BW = ODR/2). Which kind of data is

stored in the acceleration data registers depends on bit (0x13) data_high_bw. If (0x13)

data_high_bw is ´0´ (´1´), then filtered (unfiltered) data is stored in the registers. Both data

streams are offset-compensated.

The bandwidth of filtered acceleration data is determined by setting the (0x10) bw bit as

followed:

Table 4: Bandwidth configuration

Bandwidth

Update Time

tut

00xxx

01000

7.81Hz

64ms

01001

15.63Hz

32ms

01010

31.25Hz

16ms

01011

62.5Hz

8ms

01100

125Hz

4ms

01101

250Hz

2ms

01110

500Hz

1ms

01111

1000Hz

0.5ms

1xxxx

*) Note: Settings 00xxx result in a bandwidth of 7.81 Hz; settings 1xxxx result in a bandwidth of

1000 Hz. It is recommended to actively set an application specific and an appropriate bandwidth

and to use the range from ´01000b´ to ´01111b´ only in order to be compatible with future

products.

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